vxl.scr

another 8051 core porocesssor vhdl source code

#!/bin/csh -f
# vxl.scr - This script compiles and simulates the RTL or gate-level code for
# the M8051 Soft Core with the deliverable test bench m8051_tb using
# a VerilogXL simulator.

set SRC_DIR  = "../rtl"
set TBS_DIR  = "."
set NET_DIR  = "../gates/synop"
set LIB_SRC  = "/eda/libraries/vendor_kits/umc/umc18_1.0_2/std_cells/design_kit/verilog/umc18.v"
set TEST     = func1
set CODE_DIR = "../../assembler/deliverable"
set REF_DIR  = "../../vhdl/sim" 
set LIS_DIR  = lis

foreach OPTION ($argv)
  switch ($OPTION)
    case -g:
      set gates
      breaksw
    case -c:
      set gui_mode
      breaksw
    default:
      echo "${0}: Unknown option ${OPTION}"
      exit 1
  endsw
end

# Create a listing repository if it does not already exist
if (!(-d ${LIS_DIR})) mkdir ${LIS_DIR}

# Set gui is requested
if ($?gui_mode) then
  set opt = ""
else
  set opt = "+gui"
endif

if ($?gates) then
  # Compile the netlist
  set libopt = "-w +define+SDF -v ${LIB_SRC}"
  set compilethis = ${NET_DIR}/m8051.v
  set TYPE = gate
else
  # Compile the source RTL
  set libopt = ""
  set compilethis = "+incdir+${SRC_DIR} -f comp.all"
  set TYPE = rtl
endif

set tb_list = "m8051_tb.v io_cell.v p0_io_cell.v io_buffer.v rom.v ram.v"

# Link the assembler code
rm -f default_rom.rom
ln -s ${CODE_DIR}/${TEST}.rom default_rom.rom

# Run the simulation
verilog $opt $tb_list $compilethis  $libopt -l vxl_${TYPE}.log 
 

# Old
# verilog -f comp.all -l vxl_rtl_c.log
# verilog -f compgate.all -v /eda/libraries/verilog/library/tsmc35_cba.lib -l vxl_gate_c.log -w +define+SDF

# Check simulation listing results against VHDL reference simulation results

if (-e ${REF_DIR}/m8051uni.ref) then
   diff -i ${REF_DIR}/m8051uni.ref m8051uni.lis > vxl.m8051uni.${TYPE}.diff
else
   echo Cannot read reference file ${REF_DIR}/m8051uni.ref
   exit(1)
endif
ls -l ${REF_DIR}/m8051uni.ref  m8051uni.lis vxl.m8051uni.${TYPE}.diff