io_buffer.v

来自「another 8051 core porocesssor vhdl sourc」· Verilog 代码 · 共 133 行

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
////////////////////////////////////////////////////////////////////////
// Copyright Mentor Graphics Corporation 1997.  All Rights Reserved.
// io_buffer.vhd /using "cells"
// Author RPD
// Date 15th April 1997
// Version 2.000
////////////////////////////////////////////////////////////////////////
module io_buffer (P0_I, P1_I, P2_I, P3_I, BUFF_FI, BUFF_MD, ALEI, PSEI,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
                  P0_OI, P1_OI, P2_OI, P3_OI, P0_C, P1_C, P2_C, P3_C,
                  FI_INPUT, MD_INPUT, ALEO, NPSEN, NALEN, 
                  P0, P1, P2, P3, ALE, PSEN);

   output [7:0] P0_I, P1_I, P2_I, P3_I;
   output [7:0] BUFF_FI, BUFF_MD;
   output       ALEI, PSEI;
   input  [7:0] P0_OI, P1_OI, P2_OI, P3_OI;
   input  [7:0] P0_C, P1_C, P2_C, P3_C;
   input  [7:0] FI_INPUT, MD_INPUT;
   input        ALEO, NPSEN, NALEN;
   inout  [7:0] P0, P1, P2, P3;
   inout        ALE, PSEN;

   wire [7:0] P0, P1, P2, P3;
   wire [7:0] P0_C, P1_C, P2_C, P3_C;
   wire [7:0] P0_I, P1_I, P2_I, P3_I;
   wire [7:0] P0_OI, P1_OI, P2_OI, P3_OI;
   wire [7:0] FI_INPUT, MD_INPUT;
   wire       ALE, PSEN, ALEI, PSEI, ALEO, NPSEN, NALEN;

   reg [7:0]  BUFF_FI, BUFF_MD;

   integer I;

   //  PORT 0 I/O CELLS  ///////////////////////////////////////////////

   p0_io_cell u1 (.I(P0_OI[0]), .O(P0_I[0]), .DIR(P0_C[0]), .IO(P0[0]));
   p0_io_cell u2 (.I(P0_OI[1]), .O(P0_I[1]), .DIR(P0_C[1]), .IO(P0[1]));
   p0_io_cell u3 (.I(P0_OI[2]), .O(P0_I[2]), .DIR(P0_C[2]), .IO(P0[2]));
   p0_io_cell u4 (.I(P0_OI[3]), .O(P0_I[3]), .DIR(P0_C[3]), .IO(P0[3]));
   p0_io_cell u5 (.I(P0_OI[4]), .O(P0_I[4]), .DIR(P0_C[4]), .IO(P0[4]));
   p0_io_cell u6 (.I(P0_OI[5]), .O(P0_I[5]), .DIR(P0_C[5]), .IO(P0[5]));
   p0_io_cell u7 (.I(P0_OI[6]), .O(P0_I[6]), .DIR(P0_C[6]), .IO(P0[6]));
   p0_io_cell u8 (.I(P0_OI[7]), .O(P0_I[7]), .DIR(P0_C[7]), .IO(P0[7]));

   //  PORT 1 I/O CELLS  ///////////////////////////////////////////////

   io_cell u9 (.I(P1_OI[0]), .O(P1_I[0]), .DIR(P1_C[0]), .IO(P1[0]));
   io_cell u10 (.I(P1_OI[1]), .O(P1_I[1]), .DIR(P1_C[1]), .IO(P1[1]));
   io_cell u11 (.I(P1_OI[2]), .O(P1_I[2]), .DIR(P1_C[2]), .IO(P1[2]));
   io_cell u12 (.I(P1_OI[3]), .O(P1_I[3]), .DIR(P1_C[3]), .IO(P1[3]));
   io_cell u13 (.I(P1_OI[4]), .O(P1_I[4]), .DIR(P1_C[4]), .IO(P1[4]));
   io_cell u14 (.I(P1_OI[5]), .O(P1_I[5]), .DIR(P1_C[5]), .IO(P1[5]));
   io_cell u15 (.I(P1_OI[6]), .O(P1_I[6]), .DIR(P1_C[6]), .IO(P1[6]));
   io_cell u16 (.I(P1_OI[7]), .O(P1_I[7]), .DIR(P1_C[7]), .IO(P1[7]));

   //  PORT 2 I/O CELLS  ///////////////////////////////////////////////

   io_cell u17 (.I(P2_OI[0]), .O(P2_I[0]), .DIR(P2_C[0]), .IO(P2[0]));
   io_cell u18 (.I(P2_OI[1]), .O(P2_I[1]), .DIR(P2_C[1]), .IO(P2[1]));
   io_cell u19 (.I(P2_OI[2]), .O(P2_I[2]), .DIR(P2_C[2]), .IO(P2[2]));
   io_cell u20 (.I(P2_OI[3]), .O(P2_I[3]), .DIR(P2_C[3]), .IO(P2[3]));
   io_cell u21 (.I(P2_OI[4]), .O(P2_I[4]), .DIR(P2_C[4]), .IO(P2[4]));
   io_cell u22 (.I(P2_OI[5]), .O(P2_I[5]), .DIR(P2_C[5]), .IO(P2[5]));
   io_cell u23 (.I(P2_OI[6]), .O(P2_I[6]), .DIR(P2_C[6]), .IO(P2[6]));
   io_cell u24 (.I(P2_OI[7]), .O(P2_I[7]), .DIR(P2_C[7]), .IO(P2[7]));

   //  PORT 3 I/O CELLS  ///////////////////////////////////////////////

   io_cell u25 (.I(P3_OI[0]), .O(P3_I[0]), .DIR(P3_C[0]), .IO(P3[0]));
   io_cell u26 (.I(P3_OI[1]), .O(P3_I[1]), .DIR(P3_C[1]), .IO(P3[1]));
   io_cell u27 (.I(P3_OI[2]), .O(P3_I[2]), .DIR(P3_C[2]), .IO(P3[2]));
   io_cell u28 (.I(P3_OI[3]), .O(P3_I[3]), .DIR(P3_C[3]), .IO(P3[3]));
   io_cell u29 (.I(P3_OI[4]), .O(P3_I[4]), .DIR(P3_C[4]), .IO(P3[4]));
   io_cell u30 (.I(P3_OI[5]), .O(P3_I[5]), .DIR(P3_C[5]), .IO(P3[5]));
   io_cell u31 (.I(P3_OI[6]), .O(P3_I[6]), .DIR(P3_C[6]), .IO(P3[6]));
   io_cell u32 (.I(P3_OI[7]), .O(P3_I[7]), .DIR(P3_C[7]), .IO(P3[7]));

   //  CONTROL SIGNAL I/O CELLS  ///////////////////////////////////////

   io_cell u33 (.I(ALEO), .O(ALEI), .DIR(NALEN), .IO(ALE));
   io_cell u34 (.I(NPSEN), .O(PSEI), .DIR(NALEN), .IO(PSEN));

   //  INTERCONNECT INPUT BUFFERS  /////////////////////////////////////

always @(FI_INPUT)
   for (I=0; I <= 7; I = I + 1)
      case (FI_INPUT[I])
         1'b0, 1'b1:   BUFF_FI[I] = FI_INPUT[I];
         default:      BUFF_FI[I] = 1'bx;
      endcase

always @(MD_INPUT)
   for (I=0; I <= 7; I = I + 1)
      case (MD_INPUT[I])
         1'b0, 1'b1:   BUFF_MD[I] = MD_INPUT[I];
         default:      BUFF_MD[I] = 1'bx;
      endcase

   /////////////////////////////////////////////////////////////////////
endmodule