m8051_tb.v

来自「another 8051 core porocesssor vhdl sourc」· Verilog 代码 · 共 373 行

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
////////////////////////////////////////////////////////////////////////
// Demonstration Test Bench for M8051 Soft Core
//Copyright Mentor Graphics Corporation and Licensors 1999. All Rights Reserved.
//2.000
//*********************************************************************
// %W%  %G%   SCCS Version Control //
// File	      :   m8051_tb.v
// Created on :   July 2nd 1996
// Purpose    :   TEST BENCH
// Version    :   2.000
// Mod_Date   :   29th April 1997
// Mod_Hist   :   2.000 Revised MegaMacro interface, download mode
//                      demonstrated, external RAM and external SFR
//                      models included.  Listing file formats revised.
//                      Internal memory inputs buffered to eliminate Zs.
//                      ALEI & PSEI contention fixed.
//                      Simulator reset mismatches confined to vector 0.
//                      Self-checking function removed.	
//*********************************************************************
// Hierarchy record :
// called by            :   none
// calls to:
// m8051.vhd            :       m8051 Model
// tbs_dec              :       supporting function calls etc
// ram.vhd              :       RAM model
// rom.vhd              :       ROM model
// IO_buffer            :       Tristate buffers models        
//*********************************************************************
`include "speed.v"

module m8051_tb;
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
   parameter ESFR_ADDR = 8'b11101000;
//    parameter point1 = `tick * 0.1;
//    parameter point9 = `tick * 0.9;

   wire [7:0] AE;
   wire [7:0] AI;
   tri1  ALE;
   wire  ALEI;
   wire [7:0] BE;
   wire [7:0] BI;
   reg [0:71] birchars;
   reg [0:71] bircharsref;
   reg  birfault;
   reg  birfaultflag;
   reg  birstatus;
   reg [23:1] birtemprefchars;
   wire [7:0] CE;
   wire [7:0] CI;
   wire [7:0] DE;
   wire [7:0] DI;
   wire  DLM;
   reg [7:0] ESFR;
   reg [15:0] EXT_ADDR;
   wire [7:0] FA;
   wire [7:0] FI;
   reg [7:0] FI_INPUT;
   wire [7:0] FO;
   wire  IDLE;

   integer resultsbir;
   integer resultsuni;
   integer i;
   integer j;
   integer line_count;

   wire [15:0] M;
   wire [7:0] MD;
   wire [7:0] MD_INPUT;
   wire  NALEN;
   wire  ALEO;
   reg   NEA;
   reg  NESFR;
   wire  NFOE;
   wire  NFWE;
   wire  NMOE;
   wire  NMWE;
   wire  NPSEN;
   wire  NSFROE;
   wire  NSFRWE;
   reg  NX1;
   reg  NX2;
   reg  NXTAL1;
   wire [7:0] OA;
   wire [7:0] OB;
   wire [7:0] OC;
   wire [7:0] OD;
   tri [7:0] P0;
   tri1 [7:0] P1;
   tri1 [7:0] P2;
   tri1 [7:0] P3;
   wire  PSEI;
   tri1  PSEN;
   wire [7:0] RAM_DATA;
   reg  RST;
   reg [0:559] unichars;
   wire  unused0;
   wire  unused1;
   integer  vector;
   integer birlinenum;
   integer unilinenum;
   wire  XOFF;
   reg  XTAL2;

   reg [7:0] P0_STIMULUS;
   reg [7:0] P1_STIMULUS;
   reg [7:0] P2_STIMULUS;
   reg [7:0] P3_STIMULUS;
   reg ALE_STIMULUS;
   reg PSEN_STIMULUS;

   time simtime;

  `include "tbs_dec.v"


   assign unused1 = 1'b1;
   assign unused0 = 1'b0;
   assign P0 = P0_STIMULUS;
   assign P1 = P1_STIMULUS;
   assign P2 = P2_STIMULUS;
   assign P3 = P3_STIMULUS;
   assign ALE = ALE_STIMULUS;
   assign PSEN = PSEN_STIMULUS;
   
   initial
   begin
      resultsbir = $fopen("m8051bir.lis");
      resultsuni = $fopen("m8051uni.lis");
      i = 1;
      XTAL2 = 1'b0;
   end

// Reset test chip model. Reset period is two machine cycles long.
   initial
   begin : reset_gen
      P0_STIMULUS <= 8'bzzzzzzzz;
      P1_STIMULUS <= 8'bzzzzzzzz;
      P2_STIMULUS <= 8'bzzzzzzzz;
      P3_STIMULUS <= 8'bzzzzzzzz;
      NEA <= 1'b1;
      RST <= 1'b1;
      #(`tick * 48);
      RST <= 1'b0;
      #(`tick * 74192) $finish;           // End simulation here
   end
 
 //*********************************************************************
 // Download Mode stimuli
   initial
   begin : dlm_stimuli
      ALE_STIMULUS <= 1'bz;
      PSEN_STIMULUS <= 1'bz;
      P0_STIMULUS <= 8'bzzzzzzzz;
      P3_STIMULUS[7] <= 1'bz;
      P3_STIMULUS[6] <= 1'bz;
      // allow program counter to reset
      #(`tick * 8);
      // enter download mode
      ALE_STIMULUS <= 1'b0;
      PSEN_STIMULUS <= 1'b0;
      #(`tick * 4);
      // set up dummy write data
      P0_STIMULUS <= 8'b10101011;
      #(`tick * 2);
      // assert DLM write strobe
      P3_STIMULUS[6] <= 1'b0;
      #(`tick * 6);
      P3_STIMULUS[6] <= 1'bz;
      #(`tick * 2);
      // release port 0
      P0_STIMULUS <= 8'bzzzzzzzz;
      #(`tick * 4);
      // assert DLM read strobe
      P3_STIMULUS[7] <= 1'b0;
      #(`tick * 6);
      P3_STIMULUS[7] <= 1'bz;
      // wait to see program counter increment
      #(`tick * 10);
      // exit download mode
      ALE_STIMULUS <= 1'bz;
      PSEN_STIMULUS <= 1'bz;
   // this process remains inactive for the remainder of the simulation
   end
//*********************************************************************
// loop serial interface transmit pin to serial interface receive input
always @(P3)
begin
   P3_STIMULUS[0] <= !P3[7] ? P3[1]: 1'bz;
end

   //*******************************************************************
 io_buffer u1 (.P0_I(AI), .P1_I(BI), .P2_I(CI), .P3_I(DI),
               .ALEI(ALEI), .PSEI(PSEI),
               .P0_OI(OA), .P1_OI(OB), .P2_OI(OC), .P3_OI(OD),
               .ALEO(ALEO), .NPSEN(NPSEN),
               .P0_C(AE), .P1_C(BE), .P2_C(CE), .P3_C(DE),
               .NALEN(NALEN),
               .P0(P0), .P1(P1), .P2(P2), .P3(P3),
               .ALE(ALE), .PSEN(PSEN),
               .BUFF_FI(FI), .FI_INPUT(FI_INPUT),
               .BUFF_MD(MD), .MD_INPUT(MD_INPUT));
//*********************************************************************
   m8051 u2 (.AE(AE), .BE(BE), .CE(CE), .DE(DE), .FA(FA),
               .FO(FO), .M(M), .OA(OA), .OB(OB), .OC(OC), .OD(OD),
               .AI(AI), .BI(BI), .CI(CI), .DI(DI),
               .FI(FI), .MD(MD), .ALE(ALEO),
               .DLM(DLM), .NALEN(NALEN), .NFOE(NFOE),
               .NFWE(NFWE), .NSFRWE(NSFRWE), .NSFROE(NSFROE),
               .NMOE(NMOE), .NMWE(NMWE), .NPSEN(NPSEN),
               .IDLE(IDLE), .XOFF(XOFF), .ALEI(ALEI),
               .NEA(NEA), .NESFR(NESFR), .NX1(NX1),
               .NX2(NX2), .PSEI(PSEI), .RST(RST));
   //*******************************************************************
   rom u3 (.out_data(MD_INPUT), .address(M[11:0]), .ncs(unused0),
           .nromrd(NMOE));
   //*******************************************************************
   ram u4 (.data_out(RAM_DATA), .address(FA), .data_in(FO),
          .nrawr(NFWE), .nrard(NFOE), .ncs(unused0));
   //*******************************************************************
   // external RAM model for MOVX instructions, disabled during download
   // mode in order to avoid port 0 contentions.
   ram u7 (.data_out(P0), .address(EXT_ADDR[7:0]),
      .data_in(P0), .nrawr(P3[6]),
      .nrard(P3[7]), .ncs(DLM));
   //*******************************************************************

//*********************************************************************
// Test Bench starts here.
//*********************************************************************

//*********************************************************************
// Clock generation
// free running clock
   initial
   forever
      begin : clk_cycle
         NXTAL1 <= 1'b0;
         # `tick;
         NXTAL1 <= 1'b1;
         # `tick;
      end
//**********************************************************************
// Clock gating for power down modes
   always @ (NXTAL1 or IDLE or XOFF)
   begin : gate_clocks
      NX1 <= NXTAL1 || XOFF;
      NX2 <= NXTAL1 || XOFF || IDLE;
   end
   //*******************************************************************
 // External data memory address latch
   always @ (ALE or P0)
   begin : address_latch
      if (ALE == 1'b1)
      begin
         EXT_ADDR[7:0] <= P0;
      end
      EXT_ADDR[15:8] <= P2;
   end
   //******************************************************************
   // External Special Function Register Address Decoder
   always @ (FA)
   begin : ext_sfr_decoder
      if (FA == ESFR_ADDR)
      begin
         NESFR <= 1'b0;
      end
      else
      begin
         NESFR <= 1'b1;
      end
   end
   //*******************************************************************
 // External Special Function Register
   always @ (posedge NX2)
   begin : ext_sfr
      if ((NESFR || NSFRWE) == 1'b0)
      begin
         ESFR <= FO;
      end
   end
   //*******************************************************************
   // External Special Function Register Data Multiplexer
   // default condition
   always @ (NSFROE or ESFR or RAM_DATA)
   begin : ext_sfr_mux
      if (NSFROE == 1'b1)
      begin
         FI_INPUT <= RAM_DATA;
      end
      else
      begin
         FI_INPUT <= ESFR;
      end
   end

   //Test bench vector file handling
   //*******************************************************************
   initial
   begin : strobeout      
      line_count =0;
      birlinenum =0;
      unilinenum =0;
      birtitle_out;
      unititle_out;
      vector = 0;
      while (1'b1)
      begin
         line_count = line_count + 1;
         if (line_count == 40)
         begin
            birtitle_out;
            unititle_out;
            line_count = 0;
         end
         //wait for = 90% of half cycle		
         # `point9;
         vector <= vector+1;
            birdata_out;
            unidata_out;
            birlinenum = birlinenum +1;
            unilinenum = unilinenum +1;
         //wait for = half a cycle
         # `tick;
         vector = vector+1;
            birdata_out;
            unidata_out;
        //wait for = 10% of half cycle	
         # `point1;
      end
   end
//*********************************************************************  
//SDF Back Annotation
`ifdef SDF
initial
$sdf_annotate("../gates/synop/m8051.sdf",u2,,"sdf.log","TYPICAL","0.5:1:2.0","FROM_TYPICAL");
`endif

//*********************************************************************  
endmodule