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📄 io_cell.v

📁 another 8051 core porocesssor vhdl source code
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//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      ///////////////////////////////////////////////////////////////////////// %W%  %G%   SCCS Version Control// File			: io_cell.v// Author		: K Dennis// Library		: WORK// Created on		: July 5th 1996// Purpose		: Simple tri-state io buffer model//			: test chip// Version 		: 1.002// Mod_Date		: 16,iv.97 RPD signals converted to upper case// Mod_Hist		://// (C) Copyright Mentor Graphics Corporation 1997. All rights reserved.// V1.002///////////////////////////////////////////////////////////////////////Hierarchy record	://Called by		://      		:m8051_tb.v and variants//Calls to		:none//			://///////////////////////////////////////////////////////////////////module io_cell (O, I, DIR, IO);//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      //   output  O;   input  I;   input  DIR;   inout  IO;   tri1  IO;   reg TRIOUT;///////////////////////////////////////////////////////////////////////DIR is direction control, 0 is output, 1 is input, X or Z produce X//I is input internal to device.//O is output internal to device//IO is bidirectional port external to buffer. /////////////////////////////////////////////////////////////////////buf    U2 (O,IO);/////////////////////////////////////////////////////////////////////always @ (DIR or I or IO)begin   if (DIR == 1'b0)         TRIOUT = I;   else      begin         if (DIR == 1'b1)            TRIOUT = 1'bz;         else            TRIOUT = 1'bx;      endend/////////////////////////////////////////////////////////////////////assign IO = TRIOUT;/////////////////////////////////////////////////////////////////////endmodule

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