m8051.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //

module m3s001bo ( STATD, CYC, LCYC, DIV2CK1, DIV2CK2, S_EN, T_EN, STATE12, RST, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
    GOCYC2, MULDIV, NX1, NX2, PCON );
output [6:1] STATD;
output [3:1] CYC;
input  [0:0] PCON;
input  RST, GOCYC2, MULDIV, NX1, NX2;
output LCYC, DIV2CK1, DIV2CK2, S_EN, T_EN, STATE12;
    wire LDV2CK293, SMA, SMF, SMD, Q5, n_138, SMC, SMB, Q4, SME, n427, n464, 
        n3988, n3989, n3990, n3991, n3992, n3993, n3995, n3996, n3997, n3998, 
        n3999, n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, 
        n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, 
        n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, 
        n4030, n4031, n4032, n4033, n4034, net77, net78, net79, net80, net81, 
        net82, net84, net95;
    BUF_2 U176 ( .Z(DIV2CK1), .A(n_138) );
    NAND2_1 U177 ( .Z(n4006), .A0(MULDIV), .A1(n3999) );
    NOR2_1 U178 ( .Z(n4003), .A0(n4010), .A1(CYC[2]) );
    NOR2_1 U179 ( .Z(n4014), .A0(SMC), .A1(SMA) );
    NOR2_1 U180 ( .Z(n4013), .A0(SMB), .A1(SMD) );
    NAND2_1 U181 ( .Z(n4004), .A0(SMF), .A1(n4011) );
    NAND2_1 U182 ( .Z(n4002), .A0(n3998), .A1(n3999) );
    OAI21_1 U183 ( .Z(n4008), .A1(MULDIV), .A2(n3999), .B(n4015) );
    INV_1 U184 ( .Z(CYC[3]), .A(n4015) );
    MUXI21_2 U185 ( .Z(T_EN), .A0(n3990), .A1(n3989), .S(n_138) );
    INV_4 U186 ( .Z(CYC[1]), .A(n3993) );
    NOR3B1_1 U187 ( .Z(n427), .A0(n4003), .A1(n4004), .A2(MULDIV) );
    AOI21_1 U188 ( .Z(n4024), .A1(n4005), .A2(n4006), .B(n3997) );
    NOR3B1_1 U189 ( .Z(n464), .A0(n3996), .A1(n4002), .A2(GOCYC2) );
    INV_1 U190 ( .Z(n4005), .A(n4004) );
    NOR2B1_1 U191 ( .Z(n4007), .A0(n4008), .A1(GOCYC2) );
    NOR2_1 U192 ( .Z(n4009), .A0(DIV2CK2), .A1(n3988) );
    INV_1 U193 ( .Z(n4011), .A(DIV2CK2) );
    OR2_1 U194 ( .Z(n3993), .A0(Q4), .A1(Q5) );
    AND2_4 U195 ( .Z(CYC[2]), .A0(Q4), .A1(n3997) );
    AND2_1 U196 ( .Z(n3998), .A0(n4001), .A1(n4011) );
    NAND2_1 U197 ( .Z(LDV2CK293), .A0(DIV2CK1), .A1(n4001) );
    INV_1 U198 ( .Z(n4001), .A(PCON) );
    NOR2B1_1 U199 ( .Z(n4018), .A0(n4005), .A1(Q4) );
    NOR2_1 U200 ( .Z(n4010), .A0(Q4), .A1(n3997) );
    NAND2_1 U201 ( .Z(n4015), .A0(Q4), .A1(Q5) );
    DFFQ_RB_1 S_EN_reg ( .Q(S_EN), .D(SME), .CLK(NX1), .RB(n4016) );
    INV_3 U202 ( .Z(n4016), .A(RST) );
    DFF_RB_2 STATD_reg_2_ ( .Q(STATD[2]), .QB(net81), .D(n4030), .CLK(NX2), 
        .RB(n4016) );
    DFF_RB_2 STATD_reg_1_ ( .Q(STATD[1]), .QB(net82), .D(n4029), .CLK(NX2), 
        .RB(n4016) );
    DFF_RB_2 STATD_reg_6_ ( .Q(STATD[6]), .QB(net77), .D(n4034), .CLK(NX2), 
        .RB(n4016) );
    DFF_RB_2 STATD_reg_4_ ( .Q(STATD[4]), .QB(net79), .D(n4032), .CLK(NX2), 
        .RB(n4016) );
    DFF_RB_4 STATD_reg_5_ ( .Q(STATD[5]), .QB(net78), .D(n4033), .CLK(NX2), 
        .RB(n4016) );
    MUXI21_1 U203 ( .Z(n4034), .A0(net77), .A1(n3989), .S(n3998) );
    MUXI21_1 U204 ( .Z(n4033), .A0(net78), .A1(n3991), .S(n3998) );
    MUXI21_1 U205 ( .Z(n4032), .A0(net79), .A1(n3992), .S(n3998) );
    MUXI21_1 U206 ( .Z(n4031), .A0(net80), .A1(n3990), .S(n3998) );
    MUXI21_1 U207 ( .Z(n4030), .A0(net81), .A1(n3988), .S(n3998) );
    MUXI21_1 U208 ( .Z(n4029), .A0(net82), .A1(n3996), .S(n3998) );
    MUXI21_1 U209 ( .Z(n4028), .A0(n3991), .A1(n3989), .S(DIV2CK1) );
    MUXI21_1 U210 ( .Z(n4027), .A0(net84), .A1(n3996), .S(DIV2CK1) );
    MUXI21_1 U211 ( .Z(n4026), .A0(n3996), .A1(n3988), .S(DIV2CK1) );
    MUXI21_1 U212 ( .Z(n4023), .A0(n3990), .A1(n3992), .S(DIV2CK1) );
    MUXI21_1 U213 ( .Z(n4022), .A0(n4012), .A1(n3996), .S(DIV2CK1) );
    MUXI21_1 U214 ( .Z(n4021), .A0(n3988), .A1(n3990), .S(DIV2CK1) );
    MUXI21_1 U215 ( .Z(n4020), .A0(n3992), .A1(n3991), .S(DIV2CK1) );
    MUXI21_1 U216 ( .Z(n4017), .A0(net95), .A1(n4007), .S(n4009) );
    NAND3B1_1 U217 ( .Z(n4012), .A0(n4013), .A1(n4014), .A2(SMF) );
    DFF_RB_1 STATD_reg_3_ ( .Q(STATD[3]), .QB(net80), .D(n4031), .CLK(NX2), 
        .RB(n4016) );
    DFF_RB_1 SME_reg ( .Q(SME), .QB(n3989), .D(n4028), .CLK(NX1), .RB(n4016)
         );
    DFF_RB_1 STATE12_reg ( .Q(STATE12), .QB(net84), .D(n4027), .CLK(NX1), .RB(
        n4016) );
    DFF_RB_1 SMA_reg ( .Q(SMA), .QB(n3988), .D(n4026), .CLK(NX1), .RB(n4016)
         );
    DFF_RB_1 Q5_reg ( .Q(Q5), .QB(n3997), .D(n4025), .CLK(NX2), .RB(n4016) );
    DFF_RB_1 LDV2CK1_reg ( .Q(n_138), .QB(n3995), .D(n3995), .CLK(NX1), .RB(
        n4016) );
    DFF_RB_1 SMC_reg ( .Q(SMC), .QB(n3992), .D(n4023), .CLK(NX1), .RB(n4016)
         );
    DFF_RB_1 SMF_reg ( .Q(SMF), .QB(n3996), .D(n4022), .CLK(NX1), .RB(n4016)
         );
    DFF_RB_1 SMB_reg ( .Q(SMB), .QB(n3990), .D(n4021), .CLK(NX1), .RB(n4016)
         );
    DFF_RB_1 SMD_reg ( .Q(SMD), .QB(n3991), .D(n4020), .CLK(NX1), .RB(n4016)
         );
    DFF_RB_1 Q4_reg ( .Q(Q4), .QB(n3999), .D(n4019), .CLK(NX2), .RB(n4016) );
    DFF_SB_1 LCYC_reg ( .Q(LCYC), .QB(net95), .D(n4017), .CLK(NX2), .SB(n4016)
         );
    OR2_1 U218 ( .Z(n4019), .A0(n464), .A1(n4018) );
    OR2_1 U219 ( .Z(n4025), .A0(n427), .A1(n4024) );
    DFFQ_RB_1 LDV2CK2_reg ( .Q(DIV2CK2), .D(LDV2CK293), .CLK(NX1), .RB(n4016)
         );
endmodule


module m3s003bo ( ALUDAT, CPRDDM, CO, ACO, OV, BBIT, ACLDAT, TMPDAT, ALUC, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
    ACCDAT, BIT_POSN, NMULAB, NDIVAB, DAA, ACC0 );
output [7:0] ALUDAT;
input  [9:0] ACLDAT;
input  [7:0] TMPDAT;
input  [7:7] ACCDAT;
input  [17:0] ALUC;
input  [2:0] BIT_POSN;
output [7:0] CPRDDM;
input  NMULAB, NDIVAB, DAA, ACC0;
output CO, ACO, OV, BBIT;
    wire n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, 
        n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, 
        n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, 
        n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, 
        n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, 
        n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, 
        n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, 
        n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, 
        n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, 
        n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, 
        n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, 
        n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, 
        n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, 
        n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, 
        n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, 
        n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, 
        n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, 
        n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, 
        n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, 
        n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, 
        n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, 
        n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, 
        n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, 
        n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, 
        n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, 
        n3911, n3912;
    OAI21_1 U17 ( .Z(n3865), .A1(n3775), .A2(n3859), .B(n3800) );
    NAND2_1 U18 ( .Z(n3859), .A0(n3670), .A1(ACLDAT[4]) );
    NAND2_1 U19 ( .Z(n3875), .A0(n3881), .A1(ACLDAT[7]) );
    NOR2B1_1 U20 ( .Z(n3699), .A0(n3700), .A1(ACLDAT[5]) );
    NOR2B1_1 U21 ( .Z(n3711), .A0(n3712), .A1(ACLDAT[1]) );
    NOR2_1 U22 ( .Z(n3872), .A0(TMPDAT[0]), .A1(TMPDAT[7]) );
    NOR2_1 U23 ( .Z(n3873), .A0(TMPDAT[6]), .A1(TMPDAT[5]) );
    NOR2_1 U24 ( .Z(n3870), .A0(TMPDAT[4]), .A1(TMPDAT[3]) );
    NOR2_1 U25 ( .Z(n3871), .A0(TMPDAT[2]), .A1(TMPDAT[1]) );
    NOR2B1_1 U26 ( .Z(n3713), .A0(n3714), .A1(ACLDAT[2]) );
    NAND2_1 U27 ( .Z(n3825), .A0(ALUC[15]), .A1(ALUC[7]) );
    NOR2B1_1 U28 ( .Z(n3717), .A0(n3718), .A1(ACLDAT[7]) );
    NAND3_1 U29 ( .Z(n3860), .A0(n3861), .A1(n3862), .A2(n3863) );
    AOI21_1 U30 ( .Z(n3864), .A1(n3863), .A2(n3865), .B(n3697) );
    NOR3_1 U31 ( .Z(n3677), .A0(n3874), .A1(n3738), .A2(n3740) );
    OAI21_1 U32 ( .Z(n3874), .A1(n3793), .A2(n3832), .B(n3875) );
    NOR2B1_1 U33 ( .Z(n3738), .A0(n3739), .A1(ACLDAT[5]) );
    NOR2B1_1 U34 ( .Z(n3740), .A0(n3741), .A1(ACLDAT[6]) );
    NOR3_1 U35 ( .Z(n3676), .A0(n3876), .A1(n3742), .A2(n3744) );
    OAI22_1 U36 ( .Z(n3876), .A1(n3791), .A2(n3836), .B1(n3792), .B2(n3834) );
    NOR2B1_1 U37 ( .Z(n3742), .A0(n3743), .A1(ACLDAT[3]) );
    NOR2B1_1 U38 ( .Z(n3744), .A0(n3745), .A1(ACLDAT[4]) );
    MUX21_1 U39 ( .Z(n3778), .A0(n3779), .A1(n3780), .S(TMPDAT[7]) );
    NOR2B1_1 U40 ( .Z(n3719), .A0(n3666), .A1(n3720) );
    INV_1 U41 ( .Z(n3720), .A(n3697) );
    NOR2B1_1 U42 ( .Z(n3697), .A0(n3698), .A1(ACLDAT[6]) );
    NOR2B1_1 U43 ( .Z(n3721), .A0(n3723), .A1(n3722) );
    MUX21_1 U44 ( .Z(n3722), .A0(n3757), .A1(n3758), .S(TMPDAT[6]) );
    OAI21_1 U45 ( .Z(n3723), .A1(n3665), .A2(n3775), .B(n3800) );
    INV_1 U46 ( .Z(n3800), .A(n3699) );
    INV_1 U47 ( .Z(n3863), .A(n3722) );
    MUX21_1 U48 ( .Z(n3775), .A0(n3776), .A1(n3777), .S(TMPDAT[5]) );
    NAND2_1 U49 ( .Z(n3898), .A0(ACLDAT[4]), .A1(n3670) );
    MUX21_1 U50 ( .Z(n3759), .A0(n3760), .A1(n3761), .S(TMPDAT[4]) );
    NAND2_1 U51 ( .Z(n3893), .A0(n3894), .A1(n3727) );
    NOR2B1_1 U52 ( .Z(n3725), .A0(n3727), .A1(n3726) );
    MUX21_1 U53 ( .Z(n3726), .A0(n3770), .A1(n3771), .S(TMPDAT[2]) );
    OAI21_1 U54 ( .Z(n3727), .A1(n3662), .A2(n3767), .B(n3798) );
    INV_1 U55 ( .Z(n3798), .A(n3711) );
    INV_1 U56 ( .Z(n3894), .A(n3726) );
    MUX21_1 U57 ( .Z(n3767), .A0(n3768), .A1(n3769), .S(TMPDAT[1]) );
    INV_1 U58 ( .Z(n3892), .A(n3709) );
    NOR2B1_1 U59 ( .Z(n3709), .A0(n3710), .A1(ACLDAT[0]) );
    NAND2_1 U60 ( .Z(n3799), .A0(n3891), .A1(n3795) );
    MUX21_1 U61 ( .Z(n3764), .A0(n3765), .A1(n3766), .S(TMPDAT[0]) );
    XOR2_1 U62 ( .Z(n3762), .A0(n3763), .A1(ALUC[5]) );
    OAI211_1 U63 ( .Z(n3763), .A1(ALUC[5]), .A2(ALUC[4]), .B(ALUC[13]), .C(
        ACLDAT[9]) );
    NOR2B1_1 U64 ( .Z(n3855), .A0(n3788), .A1(NMULAB) );