hier_setup.scr

another 8051 core porocesssor vhdl source code

/* m8051 /verilog/synth/synop/hier_setup.scr                              */
/* Copyright Mentor Graphics Corporation and Licensors 1999.                  */
/* V2.000                                                                     */
/******************************************************************************/
/* File         :       %M%                                                   */
/* Created on   :       
/* Purpose      :       This Synopsys dc_shell script constrains the M8051    */
/* Version      :       2.000                                                 */
/* Mod Date     :       %G%                                                   */
/* Mod History  :       Time constants in units of nanoseconds                */
/*              :       Cell references are for UMC 0.18um library            */
/*                                                                            */
/******************************************************************************/

current_design "m8051"

/******************************************************************************/
/*   Specify the Operating Conditions and set up the Soft Core's environment  */
/******************************************************************************/

/* set wire load model */
set_wire_load -library umc18_wireload SMALL

/* Set input port driver strength with the exception of the clock inputs      */
/* which are unlimited for trial synthesis. */

set_drive drive_of(umc18_slow/BUF_1/Z) all_inputs()

/* set output loading */
port_load = 10 * (load_of(umc18_slow/BUF_1/A))
set_load port_load all_outputs()
set_max_transition 2.5 find(design)

/******************************************************************************/
/*  Set the timing constraints                                                */
/*  For the UMC 0.18um library all time constants are in units of NANOSECONDS */
/******************************************************************************/

/* Specify the input clock period (ns) */

CLK_PERIOD = 20           /* 50 MHz */
HALF_CLOCK = 10

/* NB: Download mode uses combinatorial paths from inputs to outputs.         */
/* To enable synthesis to work at all, DATA_IN_DLY and DATA_OUT_DLY need to   */
/* be selected to allow some propagation delay from inputs to outputs,        */
/* i.e. the inequality to be satisfied is:                                    */
/* DATA_IN_DLY + DATA_OUT_DLY < CLK_PERIOD                                    */

DATA_IN_DLY = CLK_PERIOD * 0.75
DATA_OUT_DLY =  CLK_PERIOD * 0.75
/* RAM_ADD_DLY = 10 */
/* RAM_DATA_IN_DLY = 10 */
RAM_DATA_OUT_DLY = CLK_PERIOD * 0.25

/* Propagation delay for combinatorial paths from input to output is a        */
/* quarter of a clock period                                                  */
IN_OUT_PROPN_DLY = DATA_IN_DLY + DATA_OUT_DLY + (CLK_PERIOD * 0.25)

/*                */
/*Set clock period*/
/*                */
create_clock NX1 -period CLK_PERIOD -waveform {0,HALF_CLOCK}
create_clock NX2 -period CLK_PERIOD -waveform {0,HALF_CLOCK}
set_clock_skew -ideal NX1
set_clock_skew -ideal NX2
/* Assume adequate external drive on clock */
set_drive 0 NX1
set_drive 0 NX2
dont_touch_network NX1
dont_touch_network NX2
/*                     */
/* Set input delays    */
/* (of external logic) */

/* Misc inputs */
set_input_delay -clock NX1  DATA_IN_DLY RST
set_input_delay -clock NX1  DATA_IN_DLY ALEI
set_input_delay -clock NX1  DATA_IN_DLY PSEI
set_input_delay -clock NX1  DATA_IN_DLY NEA
set_input_delay -clock NX1  DATA_IN_DLY NESFR
/* I/O Ports */
set_input_delay -clock NX1  DATA_IN_DLY AI
set_input_delay -clock NX1  DATA_IN_DLY BI
set_input_delay -clock NX1  DATA_IN_DLY CI
set_input_delay -clock NX1  DATA_IN_DLY DI
/* Program memory */
set_input_delay -clock NX1  DATA_IN_DLY MD
/* Register file */
set_input_delay -clock NX1  DATA_IN_DLY FI

/*                           */
/* Set output delaysstraints */
/* (of external logic)       */

/* I/O Ports */
set_output_delay -clock NX1 DATA_OUT_DLY OA
set_output_delay -clock NX1 DATA_OUT_DLY OB
set_output_delay -clock NX1 DATA_OUT_DLY OC
set_output_delay -clock NX1 DATA_OUT_DLY OD
set_output_delay -clock NX1 DATA_OUT_DLY AE
set_output_delay -clock NX1 DATA_OUT_DLY BE
set_output_delay -clock NX1 DATA_OUT_DLY CE
set_output_delay -clock NX1 DATA_OUT_DLY DE
/* Register file address */
set_output_delay -clock NX1 DATA_OUT_DLY FA
/* Register file */
set_output_delay -clock NX1 RAM_DATA_OUT_DLY FO
/* Program address */
set_output_delay -clock NX1 DATA_OUT_DLY M
/* Misc control */
set_output_delay -clock NX1 DATA_OUT_DLY NMOE
set_output_delay -clock NX1 DATA_OUT_DLY NMWE
set_output_delay -clock NX1 DATA_OUT_DLY DLM
set_output_delay -clock NX1 DATA_OUT_DLY ALE
set_output_delay -clock NX1 DATA_OUT_DLY NPSEN
set_output_delay -clock NX1 DATA_OUT_DLY NALEN
set_output_delay -clock NX1 DATA_OUT_DLY NFWE
set_output_delay -clock NX1 DATA_OUT_DLY NFOE
set_output_delay -clock NX1 DATA_OUT_DLY NSFRWE
set_output_delay -clock NX1 DATA_OUT_DLY NSFROE
set_output_delay -clock NX1 DATA_OUT_DLY XOFF
set_output_delay -clock NX1 DATA_OUT_DLY IDLE

/* Set default delay for asynchronous paths */
set_max_delay IN_OUT_PROPN_DLY -from all_inputs() -to all_outputs()