synth.readme

another 8051 core porocesssor vhdl source code

This is the synth.readme file for the M8051 Soft Core V6.600

General
=======

It is necessary to set the target library and create the destination 
directories for the gate level netlists.  Ensure the path 
being written to during synthesis exists. Also ensure library paths etc.
are correct.

Constraints e.g. clock speed, should be changed to suit customer 
specifications.  See comments in the file hier_setup.scr for further
information on timing constraint.

Synopsys Notes
==============

Synthesis scripts are supplied for use with Synopsys Design Compiler.
These are:

   synth.scr       dc_shell compiler control script
   
   scan.scr        scan test insertion control script
 
The synthesis control script, synth.scr, calls up three other files:

hier_compile.scr   Read in RTL for synthesis and write CBA netlist.

hier_setup.scr     external constraints file which may be modified to
                   take into account external timing information.

m8051_exp.mcp      multicycle path definition file specifies known
                   multicycle paths through the design that are required
                   to be specified for 40MHz performance in the 
                   TSMC 2.1 CBA 0.35um 3V 100 deg C library.

m8051_exp.sfp      false path definition file specifies known false
                   paths through the ALU which are not used.


hier_compile.scr performs a two-pass synthesis in which the second pass is 
incremental.  The second pass is not always required depending on the
severity of external constraints. 

First primitive elements (one bit counter and ALU cells) are ungrouped
before compilation.  Then some large and relatively self-contained parts
of the whole are characterised and compiled before an overall
compilation of the soft core.  An incremental recompilation of the
soft Core is then performed.

At the end of hier_compile.scr the script directs the files to directory
locations used in Inventra's internal design flow. The output file
locations should be altered to suit the customer's directory structure.
 
The scan.scr assumes that the output from synthesis under synth.scr is 
present.
 
This design has been synthesised using Synopsys version 1999.05.
 
This version of design compiler produces the following warning which
may safely be ignored:
 
In a number of modules unconnected inputs are reported. These warnings
concern busses that have been taken into a module. These are generally
documented in the headers of the modules concerned.
 
If the target library does not contain flip-flops with both
synchronous set and reset inputs, then warnings to this affect are
generated.
 
Performance is detailed in the file perform.txt in the main M8051
directory.

Special Note

When synthesising in Verilog, problems have been reported when the
Synopsys Verilog netlist is used by Cadence layout tools. The problem
concerns "single bit" vectors used in modules. A workaround is to write
the design out in VHDL format, read it back in and then write out for
a second time in Verilog.