.synopsys_dc.setup

another 8051 core porocesssor vhdl source code

designer = "Inventra" ;
company = "Mentor Graphics";

search_path = search_path + /eda/libraries/vendor_kits/umc/umc18_1.0_2/std_cells/design_kit/design_compiler

target_library = {umc18_slow.db};
link_library = {umc18_slow.db umc18_wireload.db};
/* symbol_library = {umc18.slib}; */

synthetic_library = {} ;

plot_command = "lp -onobanner -dmickey" ;
text_print_command = "lp -onobanner -dmickey" ;

cache_read = { "/eda/synopsys_cache" } ;
cache_write = "/eda/synopsys_cache" ;
cache_read_info = "true";
cache_write_info = "true";
cache_file_chmod_octal = "666";
cache_dir_chmod_octal = "777";

edifin_autoconnect_ports = "true";
edifin_ground_net_property_name = "POWER";
edifin_ground_net_property_value = "0";
edifin_power_net_property_name = "POWER";
edifin_power_net_property_value = "1";
edifin_use_identifier_in_rename = "true";

edifout_ground_name = "__logic_0__";
edifout_ground_net_name = "NC0";
edifout_ground_net_property_name = "POWER";
edifout_ground_net_property_value = "0";
edifout_ground_pin_name = "__logic_0_pin__";
edifout_ground_port_name = "NC0";
edifout_netlist_only = "true";
edifout_power_and_ground_representation = "net";
edifout_power_name  = "__logic_1__";
edifout_power_net_name = "NC1";
edifout_power_net_property_name = "POWER";
edifout_power_net_property_value = "1";
edifout_power_pin_name  = "__logic_1_pin__";
edifout_power_port_name  = "NC1";

hdlin_latch_always_async_set_reset = TRUE;
hdlin_ff_always_sync_set_reset = TRUE;

vhdlout_architecture_name = "RTL";
vhdlout_preserve_hierarchical_types = "USER";

view_read_file_suffix  = {db, gdb, sdb, edif, edi, eqn, fnc, lsi, mif, NET, pla, st, tdl, v, vhd, vhdl, xnf} ;
view_write_file_suffix = {gdb, db, sdb, do, edif, edi, eqn, fnc, lsi, NET, neted, pla, st, tdl, v, vhd, vhdl, xnf} ;

define_design_lib WORK -path ./WORK ;
/* define_design_lib CBA_CORE -path /eda/libraries/vital/library/tsmc35_cba_synop ; */


hdl_keep_licenses = false

/******************************************************************************/
/*                   SiArc BiNMOS/CMOS-CBA (TM) setup for                     */
/*                      Design Complier - Version 3.3a                        */
/*                  ".synopsys_dc.setup" Initialization File                  */
/*            An unpublished work, Copyright (C) 1991 - 1996 SiArc.           */
/*                            All rights reserved.                            */
/*          Licensed Software - Silicon Architects(SiArc) Confidential        */
/******************************************************************************/

/* Company Name */
company = "Mentor Graphics"

/* Edif in Setup */
edifin_lib_logic_1_symbol = "vdd"
edifin_lib_logic_0_symbol = "gnd"

/* Edif out Setup */
edifout_ground_pin_name = "Y"
edifout_power_pin_name = "Y"
edifout_power_and_ground_representation = "cell"
edifout_netlist_only = "true"
edifout_no_array = "false"
edifout_multidimension_arrays = "false"


/* Name rule set for CBA */
define_name_rules CBARules	-allowed "a-z A-Z 0-9 _ [ ] ( )" \
				-first_restricted "0-9 _ [ ] ( )" \
				-last_restricted "_" -type port

define_name_rules CBARules	-allowed "a-z A-Z 0-9 _ [ ] ( )" \
				-first_restricted "0-9 _ [ ] ( )" \
				-last_restricted "_" -type net

define_name_rules CBARules	-allowed "a-z A-Z 0-9 _" \
				-first_restricted "0-9 _" \
				-last_restricted "_" -type cell
default_name_rules = CBARules
alias CBA_names "change_names -verbose -hierarchy -rules CBARules"

/* set up alias for cba commands */

alias cba_edif_out "include /eda/siarc/ds/lib/ds/synopsys/cba_edif_out.script"

alias cba_verilog_out "include /eda/siarc/ds/lib/ds/synopsys/cba_verilog_out.script"