m3s028bo.v

another 8051 core porocesssor vhdl source code

  end 

  always @(posedge NX1)
  begin : gentxclk
    if (T_EN & ~DIV2CK1)
    begin
      TXCLK <= 1'b0 ; 
    end
    else if (SETTXCLK)
    begin
      TXCLK <= 1'b1 ; 
    end  
  end 

  always @(posedge NX1)
  begin : delayten
    if (T_EN & DIV2CK1)
    begin
      SETTXCLK <= 1'b1 ; 
    end
    else
    begin
      SETTXCLK <= 1'b0 ; 
    end  
  end 

  always @(MODE0 or Q1 or CKMASK or STATE12 or RXC9 or DELCNT)
  begin : clksenab
    case (MODE0)
      1'b0 :
            begin
              TX_EN <= Q1 & DELCNT & ~CKMASK ; 
              RX_EN <= RXC9 & ~CKMASK ; 
            end
      1'b1 :
            begin
              TX_EN <= (~CKMASK) & STATE12 ; 
              RX_EN <= (~CKMASK) & STATE12 ; 
            end
      default :
            begin
              RX_EN <= 1'bx ; 
              TX_EN <= 1'bx ; 
            end
    endcase 
  end 

  always @(posedge NX1)
  begin : divby2
    if (CLEAR)
    begin
      DIVTWO <= 1'b0 ; 
    end
    else if (COUNT_EN)
    begin
      DIVTWO <= ~DIVTWO ; 
    end  
  end 

  always @(posedge NX1)
  begin : setrxc78
    if (!DIV2CK1)
    begin
      RXC7 <= (~AF) & COUNT_EN & TCI[0] ; 
      RXC8 <= (~AE) & COUNT_EN & TCI[0] ; 
      RXC9 <= (~AH) & COUNT_EN & TCI[0] ; 
    end  
  end 

  always @(posedge NX1)
  begin : txprestoplat
    if (T_EN & (~DIV2CK1))
    begin
      Q3 <= TXSTOPBIT ; 
      NEWDATA <= ~DATAEN ; 
    end  
  end 

  always @(posedge NX1)
  begin : txstopbitlat
    if (CLEAR)
    begin
      TSHIFT_IN <= 1'b0 ; 
    end
    else if (TSHIFT_EN)
    begin
      if (!NEWDATA)
      begin
        TSHIFT_IN <= Q3 ; 
      end
      else
      begin
        TSHIFT_IN <= L_SCON[3] | ~L_SCON[7] ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : setq1
    if (COUNT_EN)
    begin
      Q1 <= TCI[0] & TX_DIV[3] & TX_DIV[2] & TX_DIV[0] & ~TX_DIV[1] ; 
    end  
  end 

  always @(posedge NX1)
  begin : setq5
    if (CLEAR)
    begin
      Q5 <= 1'b0 ; 
    end
    else if (TISET)
    begin
      Q5 <= 1'b0 ; 
    end
    else if (SFRW[11])
    begin
      Q5 <= 1'b1 ; 
    end  
  end 

  always @(posedge NX1)
  begin : setq6
    if (!(T_EN & DIV2CK1))
    begin
      Q6 <= ~Q5 ; 
    end  
  end 

  always @(posedge NX1)
  begin : RB8control
    if (CLEAR)
    begin
      SELRB8 <= 1'b0 ; 
    end
    else if (RX_EN & ~DIV2CK1)
    begin
      SELRB8 <= ~BLOCK_SBUF_LD & ~MODE0 & RCV & ~FRM[0] ; 
    end  
  end 

  always @(posedge NX1)
  begin : settsend
    if (CLEAR)
    begin
      TSEND <= 1'b0 ; 
    end
    else if (((T_EN & (~Q5) & ~DIV2CK1) | Q6))
    begin
      TSEND <= 1'b0 ; 
    end
    else if (TX_EN & ~DIV2CK1)
    begin
      TSEND <= 1'b1 ; 
    end  
  end 

  always @(posedge NX1)
  begin : setdataen
    if (((T_EN & (~Q5) & ~DIV2CK1) | Q6))
    begin
      DATAEN <= 1'b0 ; 
    end
    else if (TX_EN & ~DIV2CK1)
    begin
      if (!(DATAEN | MODE0))
      begin
        DATAEN <= TSEND ; 
      end
      else
      begin
        DATAEN <= 1'b1 ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : settstopbit
    if (TX_EN & ~DIV2CK1)
    begin
      TXSTOPBIT <= L_SCON[7] & (~DATAEN) & ~Q6 ; 
    end  
  end 

  always @(posedge NX1)
  begin : setlastbit
    if (Q6 | CLEAR)
    begin
      TXLASTBIT <= 1'b0 ; 
    end
    else if ((TX_EN & DIV2CK1))
    begin
      TXLASTBIT <= TSEND & QLOW & (~TSHIFT_IN) & (~TXSTOPBIT) ; 
    end  
  end 

  always @(posedge NX1)
  begin : settxend
    if (CLEAR | Q6)
    begin
      TXEND <= 1'b0 ; 
    end
    else if ((TX_EN & DIV2CK1))
    begin
      TXEND <= TXLASTBIT ; 
    end  
  end 

  always @(posedge NX1)
  begin : setrstqs
    if (CLEAR)
    begin
      RSTQ1 <= 1'b0 ; 
    end
    else if (COUNT_EN)
    begin
      if (TCI[0])
      begin
        RSTQ1 <= RCV | ~RX_DIN ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : setrcv
    if (CLEAR | !(L_SCON[4]))
    begin
      RCV <= 1'b0 ; 
    end
    else if (RST16C)
    begin
      RCV <= 1'b1 ; 
    end
    else if (RX_EN & ~DIV2CK1)
    begin
      RCV <= (RCV & (~(FLST | (RCV & CLR_RCV)))) | ~SWREC ; 
    end  
  end 

  always @(posedge NX1)
  begin : delbitclearrcv
    if (CLEAR)
    begin
      DELCLRRCV <= 1'b0 ; 
    end
    else if (RSHIFT_EN)
    begin
      DELCLRRCV <= ~FRM[0] ; 
    end  
  end 

  always @(DELCLRRCV or FRM or L_SCON)
  begin : muxclrrcv
    if (!(L_SCON[7]))
    begin
      CLR_RCV <= ~FRM[0] ; 
    end
    else
    begin
      CLR_RCV <= DELCLRRCV ; 
    end 
  end 

  always @(posedge NX1)
  begin : setdelrcv
    if (T_EN & !DIV2CK1)
    begin
      DELRCV <= RCV ; 
    end  
  end 

  always @(posedge NX1)
  begin : setswrec
    if (T_EN & ~DIV2CK1)
    begin
      SWREC <= RCV | LL_SCON[0] | (~L_SCON[4]) | (~MODE0) ; 
    end  
  end 

  always @(posedge NX1)
  begin : setmajq1
    if (RXC7)
    begin
      MAJQ1 <= RX_DIN ; 
    end  
  end 

  always @(posedge NX1)
  begin : setmajq2
    if (RXC8)
    begin
      MAJQ2 <= RX_DIN ; 
    end  
  end 

  always @(posedge NX1)
  begin : sample
    // 9th bit latch
    RX_DIN <= DI[0] ;  
  end 

  always @(RX_DIN or MAJQ2 or MAJQ1)
  begin : majin
    MAJOUT <= (MAJQ1 & RX_DIN) | (MAJQ1 & MAJQ2) | (MAJQ2 & RX_DIN) ; 
  end 

  always @(posedge NX1)
  begin : setbitin
    if (RSHIFT_EN & !DIV2CK1)
    begin
      if (!LORCV)
      begin
        BITIN <= MAJOUT ; 
      end
      else
      begin
        BITIN <= 1'b1 ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : m0in
    if (S_EN & !DIV2CK1)
    begin
      MODE0_IN <= RX_DIN ; 
    end  
  end 

  always @(MODE0 or MODE0_IN or BITIN)
  begin : muxrshiftin
    if (!MODE0)
    begin
      RSHIFT_IN <= BITIN ; 
    end
    else
    begin
      RSHIFT_IN <= MODE0_IN ; 
    end 
  end 

  always @(posedge NX1)
  begin : setfsrej
    if (!RCV)
    begin
      FSREJ <= 1'b0 ; 
    end
    else if (RX_EN & !DIV2CK1)
    begin
      FSREJ <= DELRCV ; 
    end  
  end 

  always @(posedge NX1)
  begin : setsbuf
    if (CLEAR)
    begin
      SBUF <= 8'b00000000 ; 
    end
    else if (RISET & DIV2CK1)
    begin
      SBUF <= FRM ; 
    end  
  end 

  always @(posedge NX1)
  begin : setldrcv
    if (RST16C | CLEAR)
    begin
      LORCV <= 1'b1 ; 
    end
    else if (!RX_EN & !DIV2CK1)
    begin
      LORCV <= ~RCV ; 
    end  
  end 

  always @(posedge NX1)
  begin : set_end_data
    if (CLEAR | END_DATA | (RCV & ~DELRCV))
    begin
      END_DATA <= 1'b0 ; 
    end
    else if (RSHIFT_EN & RCV & (~FRM[0]) & ~DIV2CK1)
    begin
      END_DATA <= 1'b1 ; 
    end  
  end 

  always @(LL_SCON or L_SCON or LTCI or LRCI or LRITI)
  begin : localout
    // Rename divider carry outputs (LTCI & LRCI) for verilog compatibility.
    SCON[7:3] <= L_SCON ; 
    SCON[2:0] <= LL_SCON ; 
    TCI[3:1] <= LTCI ; 
    RCI[3:1] <= LRCI ; 
    RITI <= LRITI ; 
  end 
  //*********************************************************************
  //*********************************************************************
endmodule