m3s028bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//UART for M8051
//Copyright Mentor Graphics Corporation and Licensors 1999. All rights reserved.
//v1.103
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Aug. 10, 1998
// Mon Oct 12 17:48:34 1998
//
// Input file : m3s028bo.vhd
// Design name : m3s028bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s028bo.vhd
//Created on    :       15th Dec 1995
//Purpose       :       UART for M8051
//Version       :       1.103
//Mod Date      :       25th March 1999
//Mod History	:       1.103 ECN 1226 - Fix to UART receiver in mode 0
//                            ECN 1140 - RI bit in modes 2 & 3 dependency on SM2
//                      1.102 ECN 1185 - SCON.4 now disables reception at any
//                            stage
//                      1.101 _e suffix removed from entity names.
//                      1.100 ECN1053 - Serial receive mode 0 fixed
//			1.009 Redundant port removed.
//                      1.008 Rename divider carry outputs for Verilog
//                            compatibility.
//                      1.007 UART sampling time and latency fixes.
//                            Sensitivity list revisions.
//                      1.006 Port initialisation during reset
//                      1.005 Idle Mode Power Saving
//			1.004 ECN 812-9 bit mode
//                      1.003-Calling file changed to m8051.vhd
//                            LTCI bus added for verilog conversion, 
//                            no circuit change
//                      1.002-ECNs 742,743
//                      1.001(Original)
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :m3s029bo.vhd
//                      :m3s030bo.vhd
//                      :m3s031bo.vhd
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s028bo (SCON, SBUF, RITI, RXDO, TXDO, DI, RAMDI, PCON, SFRW, LOV1,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
S_EN, T_EN, STATE12, DIV2CK1, NX1, NX2, CLEAR);

  output[7:0] SCON;
  reg[7:0] SCON;
  output[7:0] SBUF;
  reg[7:0] SBUF;
  output RITI;
  reg RITI;
  output RXDO;
  reg RXDO;
  output TXDO;
  reg TXDO;
  input[0:0] DI;
  input[7:0] RAMDI;
  input[7:7] PCON;
  input[11:10] SFRW;
  input LOV1;
  input S_EN;
  input T_EN;
  input STATE12;
  input DIV2CK1;
  input NX1;
  input NX2;
  input CLEAR;

  //*********************************************************************
  //*********************************************************************
  // Component Definitions
  //*********************************************************************
  //1 up bit counter(sync clear)
  //*********************************************************************
  //TX shift reg
  //*********************************************************************
  //RX shift reg
  //*********************************************************************
  //signal definition
  //*********************************************************************
  reg COUNT_EN; 
  reg TSHIFT_EN; 
  reg TSHIFT_IN; 
  wire SOUT; 
  reg RSHIFT_EN; 
  reg RSHIFT_IN; 
  wire QLOW; 
  reg NEWDATA; 
  reg AE; 
  reg AF; 
  reg BLOCK_SBUF_LD; 
  reg AH; 
  reg TXLASTBIT; 
  reg TXEND; 
  reg TISET; 
  reg RISET; 
  reg DCKM; 
  reg CKMASK; 
  reg CLEAR16C_RX; 
  reg CLEAR16C_TX; 
  reg MODE0; 
  reg DIVTWO; 
  reg MAJOUT; 
  reg TSEND; 
  reg D0; 
  reg Q1; 
  reg Q3; 
  reg Q5; 
  reg Q6; 
  reg END_DATA; 
  reg TXSTOPBIT; 
  reg FLST; 
  reg FSREJ; 
  reg RXC7; 
  reg RXC8; 
  reg RXC9; 
  reg TXCLK; 
  reg SETTXCLK; 
  reg RSTQ1; 
  reg RX_EN; 
  reg TX_EN; 
  reg DATAEN; 
  reg RX_DIN; 
  reg CLR_RCV; 
  reg DELCLRRCV; 
  reg RCV; 
  reg DELRCV; 
  reg BITIN; 
  reg SWREC; 
  reg LORCV; 
  reg SELRB8; 
  reg RST16C; 
  reg DELRST16C; 
  reg DELCNT; 
  reg MODE0_IN; 
  reg MAJQ1; 
  reg MAJQ2; 
  reg LRITI; 
  reg[3:0] TCI; 
  reg[3:0] RCI; 
  wire[3:0] TX_DIV; 
  wire[3:0] RX_DIV; 
  wire[3:1] LTCI; 
  wire[3:1] LRCI; 
  wire[7:0] FRM; 
  reg[7:3] L_SCON; 
  reg[2:0] LL_SCON; 
  //*********************************************************************
  //*********************************************************************
  //port mapping
  //*********************************************************************
  //*********************************************************************
  //MSBit TX generator
  m3s029bo U1 (.CO(open), .Q(TX_DIV[3]), .CI(TCI[3]), .CLEAR(CLEAR16C_TX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  // TX generator
  m3s029bo U2 (.CO(LTCI[3]), .Q(TX_DIV[2]), .CI(TCI[2]), .CLEAR(CLEAR16C_TX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  // TX generator
  m3s029bo U3 (.CO(LTCI[2]), .Q(TX_DIV[1]), .CI(TCI[1]), .CLEAR(CLEAR16C_TX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  //LSBit TX generator
  m3s029bo U4 (.CO(LTCI[1]), .Q(TX_DIV[0]), .CI(TCI[0]), .CLEAR(CLEAR16C_TX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  //MSBit RX generator
  m3s029bo U5 (.CO(open), .Q(RX_DIV[3]), .CI(RCI[3]), .CLEAR(CLEAR16C_RX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  // RX generator
  m3s029bo U6 (.CO(LRCI[3]), .Q(RX_DIV[2]), .CI(RCI[2]), .CLEAR(CLEAR16C_RX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  //RX generator
  m3s029bo U7 (.CO(LRCI[2]), .Q(RX_DIV[1]), .CI(RCI[1]), .CLEAR(CLEAR16C_RX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  //LSBit RX generator
  m3s029bo U8 (.CO(LRCI[1]), .Q(RX_DIV[0]), .CI(TCI[0]), .CLEAR(CLEAR16C_RX),
  .COUNT_EN(COUNT_EN), .NX1(NX1)); 
  //*********************************************************************
  //TX Buffer
  m3s030bo U9 (.SOUT(SOUT), .QLOW(QLOW), .NEWDATA(NEWDATA), .CLEAR(CLEAR),
  .TSHIFT_EN(TSHIFT_EN), .TSHIFT_IN(TSHIFT_IN), .NX1(NX1), .RAMDI(RAMDI)); 
  //*********************************************************************
  //RX Buffer
  m3s031bo U10 (.FRM(FRM), .D0(D0), .LORCV(LORCV), .RSHIFT_EN(RSHIFT_EN),
  .RSHIFT_IN(RSHIFT_IN), .NX1(NX1)); 

  always @(posedge NX2)
  begin : setsconhi
    if (CLEAR)
    begin
      L_SCON[7:3] <= 5'b00000 ; 
    end
    else
    begin
      if (SFRW[10])
      begin
        L_SCON[7:3] <= RAMDI[7:3] ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : setsconlo
    if (CLEAR)
    begin
      LL_SCON[2:0] <= 3'b000 ; 
    end
    else
    begin
      if (SFRW[10])
      begin
        LL_SCON[2] <= RAMDI[2] ; 
      end
      else if (RISET & SELRB8)
      begin
        if (!DELRCV)
        begin
          if (!(L_SCON[7]))
          begin
            if (L_SCON[6] & ~L_SCON[5])
            begin
              LL_SCON[2] <= MAJOUT ; 
            end 
          end
          else
          begin
            LL_SCON[2] <= BITIN ; 
          end 
        end
        else
        begin
          LL_SCON[2] <= MAJOUT ; 
        end 
      end 
      if (TISET)
      begin
        LL_SCON[1] <= 1'b1 ; 
      end
      else if (SFRW[10])
      begin
        LL_SCON[1] <= RAMDI[1] ; 
      end 
      if (RISET)
      begin
        LL_SCON[0] <= 1'b1 ; 
      end
      else if (SFRW[10])
      begin
        LL_SCON[0] <= RAMDI[0] ; 
      end 
    end  
  end 

  always @(RAMDI or L_SCON or LL_SCON or SFRW or CLEAR or RST16C or DIVTWO or 
   PCON or NEWDATA or TSHIFT_EN)
  begin : gen1
    DCKM <= ((RAMDI[7] ^ L_SCON[7]) | (RAMDI[7] ^ L_SCON[7])) & SFRW[10] ; 
    MODE0 <= ~(L_SCON[6] | L_SCON[7]) ; 
    CLEAR16C_RX <= CLEAR | RST16C ; 
    CLEAR16C_TX <= CLEAR | (TSHIFT_EN & NEWDATA) ; 
    TCI[0] <= DIVTWO | PCON[7] ; 
  end 

  always @(TX_EN or DIV2CK1 or DATAEN or SOUT or MODE0 or TSEND or RCV or 
   SFRW or TXCLK or TXLASTBIT or TXEND)
  begin : gen2
    TSHIFT_EN <= (TX_EN & (~DIV2CK1) & DATAEN) | SFRW[11] ; 
    RXDO <= SOUT | (~MODE0) | (~TSEND) ; 
    TXDO <= ~((MODE0 & (~TXCLK) & (RCV | TSEND)) | ((~MODE0) & TSEND & (~
    TXLASTBIT) & ~(DATAEN & SOUT))) ; 
    D0 <= ~MODE0 ; 
    TISET <= (MODE0 & TXEND) | (TXLASTBIT & ~MODE0) ; 
  end 

  always @(RSTQ1 or RCV or RX_DIN or L_SCON or MODE0)
  begin : gen3
    RST16C <= (~RSTQ1) & (RCV | ~RX_DIN) & L_SCON[4] & ~MODE0 ; 
  end 

  always @(posedge NX1)
  begin : set_riti
    if (CLEAR)
    begin
      LRITI <= 1'b0 ; 
    end
    else if (MODE0)
    begin
      LRITI <= LL_SCON[0] | LL_SCON[1] ; 
    end
    else if (S_EN & DIV2CK1)
    begin
      LRITI <= RISET | TISET | LL_SCON[0] | LL_SCON[1] ; 
    end
    else if (!(LL_SCON[0] | LL_SCON[1]))
    begin
      LRITI <= 1'b0 ; 
    end  
  end 

  always @(posedge NX1)
  begin : setdelrst
    if (COUNT_EN)
    begin
      DELRST16C <= RST16C ; 
    end  
  end 

  always @(DELRCV or SWREC or RX_EN or DELRST16C or DIV2CK1 or CLEAR or LORCV 
  or 
   CLR_RCV or L_SCON or END_DATA or BLOCK_SBUF_LD or MODE0)
  begin : gen4
    RSHIFT_EN <= ((DELRCV | ~SWREC) & RX_EN & ~DIV2CK1 & (~CLR_RCV | ~L_SCON[
    7])) | (DELRST16C & LORCV) | CLEAR ; 
    RISET <= END_DATA & (MODE0 | ~BLOCK_SBUF_LD) ; 
  end 

  always @(FSREJ or RCV or MODE0 or MAJOUT or CLEAR)
  begin : gen5
    FLST <= CLEAR | (MAJOUT & RCV & (~MODE0) & ~FSREJ) ; 
  end 

  always @(RX_DIV or CLEAR16C_RX or MAJOUT or L_SCON or LL_SCON)
  begin : misc1
    AF <= RX_DIV[3] | (~RX_DIV[2]) | RX_DIV[1] | RX_DIV[0] | CLEAR16C_RX ; 
    AE <= RX_DIV[3] | (~RX_DIV[2]) | RX_DIV[1] | (~RX_DIV[0]) | CLEAR16C_RX ; 
    AH <= RX_DIV[3] | (~RX_DIV[2]) | (~RX_DIV[1]) | RX_DIV[0] | CLEAR16C_RX ; 
    BLOCK_SBUF_LD <= ((~MAJOUT) & L_SCON[5]) | LL_SCON[0] ; 
  end 

  always @(L_SCON or CKMASK or DIV2CK1 or LOV1)
  begin : countrxtx
    COUNT_EN <= ((L_SCON[6] & (~CKMASK) & LOV1) | ((~L_SCON[6]) & (~CKMASK)))
    & ~DIV2CK1 ; 
  end 

  always @(posedge NX1)
  begin : setdelcnt
    if (!DIV2CK1)
    begin
      DELCNT <= COUNT_EN ; 
    end  
  end 

  always @(posedge NX1)
  begin : setckmask
    if (!(SFRW[10]))
    begin
      CKMASK <= DCKM ; 
    end