m3s009bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// Register Write Data Multiplexer sub-block of M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.006
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:04 1998
//
// Input file : m3s009bo.vhd
// Design name : m3s009bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s009bo.vhd
//Created on    :       11th October 1995
//Purpose       :       Register multiplexor sub-block of m8051
//Version       :       1.006
//Mod Date      :       2nd April 1998 
//Mod History	:       1.006 _e suffix removed from entity names.
//                      1.005 STATDs 7-12 abandoned.
//                      1.004 XCHD register timing retarded to S5P2
//                      1.003 Delay data change until beginning of S1P2.
//                      1.002 Timing change to LDATAB(nibble swap latch)
//                      1.001 Original
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s008bo.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//-------------------------------------------------
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s009bo (RAMDI, STACK_DATA, IMMDAT, ALUDAT, REGADD, CYC, STATD, RDAT,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
DIV2CK, NX1, RST);

  output[7:0] RAMDI;
  reg[7:0] RAMDI;
  input[15:0] STACK_DATA;
  input[7:0] IMMDAT;
  input[7:0] ALUDAT;
  input[1:0] REGADD;
  input[2:2] CYC;
  input[5:5] STATD;
  input[7:4] RDAT;
  input DIV2CK;
  input NX1;
  input RST;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg[7:0] LDATAA; 
  reg[7:4] REG_HI_NIBBLE; 
  reg STACK_MUX; 

  always @(posedge NX1 or posedge RST)
  begin : stack_mux_selector
    if (RST)
    begin
      STACK_MUX <= 1'b0 ; 
    end
    else
    begin
      // Delay write data switch over to beginning of S1P2 to avoid race
      // with NFWE at end of S6P2.
      if (DIV2CK)
      begin
        STACK_MUX <= CYC[2] ; 
      end 
    end 
  end 

  always @(STACK_DATA or STACK_MUX)
  begin : set_abus
    // Select program address byte for writing to stack during CALL and PUSH
    // instructions.
    case (STACK_MUX)
      1'b0 :
            begin
              LDATAA <= STACK_DATA[7:0] ; 
            end
      1'b1 :
            begin
              LDATAA <= STACK_DATA[15:8] ; 
            end
      default :
            begin
              LDATAA <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(REGADD or ALUDAT or IMMDAT or REG_HI_NIBBLE or LDATAA)
  begin : set_outbus
    case (REGADD[1:0])
      2'b00 :
            begin
              RAMDI <= ALUDAT ; 
            end
      2'b01 :
            begin
              RAMDI <= IMMDAT ; 
            end
      2'b10 :
            begin
              RAMDI[3:0] <= ALUDAT[3:0] ; 
              RAMDI[7:4] <= REG_HI_NIBBLE ; 
            end
      2'b11 :
            begin
              RAMDI <= LDATAA ; 
            end
      default :
            begin
              RAMDI <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(posedge NX1 or posedge RST)
  begin : upper_nibble_temp
    if (RST)
    begin
      REG_HI_NIBBLE <= 4'b0000 ; 
    end
    else
    begin
      // Temporary Data Memory Upper Nibble register
      // Used by Exchange Digit instruction (XCHD) to store dat memory nibble
      // Loads at the end of S5P2 (same as for temporary registers 1 and 2).
      if (STATD[5] & ~DIV2CK)
      begin
        REG_HI_NIBBLE <= RDAT[7:4] ; 
      end 
    end 
  end 
  //*********************************************************************
endmodule