m3s013bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//M8051 Megamacro Program Counter Next Address Multiplexer.
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:14 1998
//
// Input file : m3s013bo.vhd
// Design name : m3s013bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File          :       m3s013bo.vhd
//Created on    :       4 Jan 1996
//Purpose       :       M8051 Megamacro PC Input Data Multiplexor.
//Version       :       1.005
//Mod Date      :       2nd April 1998
//Mod History   :       1.005 _e suffix removed from entity names.
//                      1.004 Case statements exhaustively defined.
//                      1.003 MUX controls re-written for synthesis.
//                      1.002 Direct path from INTA to program counter
//                            bypassing opcode decoder to avoid
//                            unnecessary multicycle paths in decoder.
//
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s010bo
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s013bo (NEXT_PROGRAM_COUNT, VECTOR_ADDR, IMMDAT, ALUDAT, RDAT, OPC,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
NEXT_REL_PC, PCADD, NFBL, NFBH, SEL_11BIT_ADDR, INTA);

  output[15:0] NEXT_PROGRAM_COUNT;
  reg[15:0] NEXT_PROGRAM_COUNT;
  input[4:1] VECTOR_ADDR;
  input[7:0] IMMDAT;
  input[7:0] ALUDAT;
  input[7:0] RDAT;
  input[7:5] OPC;
  input[15:0] NEXT_REL_PC;
  input[2:1] PCADD;
  input NFBL;
  input NFBH;
  input SEL_11BIT_ADDR;
  input INTA;

  //*********************************************************************
  reg[2:0] L_YY; 
  reg[7:0] LOCALA; 
  reg[7:0] ALUDAT_MOD; 

  always @(PCADD or IMMDAT or RDAT or VECTOR_ADDR or ALUDAT or INTA)
  begin : setlocala
    if (INTA)
    begin
      // generate the interrupt vector
      LOCALA[0] <= VECTOR_ADDR[1] ; 
      LOCALA[1] <= VECTOR_ADDR[1] ; 
      LOCALA[2] <= 1'b0 ; 
      LOCALA[5:3] <= VECTOR_ADDR[4:2] ; 
      LOCALA[6] <= 1'b0 ; 
      LOCALA[7] <= 1'b0 ; 
    end
    else
    begin
      // Generate equivalent of mm41B
      case (PCADD[2:1])
        2'b00 :
              begin
                LOCALA <= IMMDAT ; 
              end
        2'b01 :
              begin
                LOCALA <= RDAT ; 
              end
        2'b10 :
              begin
                LOCALA <= ALUDAT ; 
              end
        2'b11 :
              begin
                LOCALA <= ALUDAT ; 
              end
        default :
              begin
                LOCALA <= 8'bXXXXXXXX ; 
              end
      endcase 
    end 
  end 

  always @(NFBL or NEXT_REL_PC or LOCALA)
  begin : set_low_addr
    // Program Counter Low Byte Alternative Source Multiplexer
    case (NFBL)
      1'b0 :
            begin
              NEXT_PROGRAM_COUNT[7:0] <= NEXT_REL_PC[7:0] ; 
            end
      1'b1 :
            begin
              NEXT_PROGRAM_COUNT[7:0] <= LOCALA ; 
            end
      default :
            begin
              NEXT_PROGRAM_COUNT[7:0] <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(SEL_11BIT_ADDR or NEXT_REL_PC or OPC)
  begin : switch_11bits
    // Use opcode to generate upper three bits of an 11-bit address.
    // Used by ACALL and AJMP instructions only.
    case (SEL_11BIT_ADDR)
      1'b0 :
            begin
              L_YY[2:0] <= NEXT_REL_PC[10:8] ; 
            end
      1'b1 :
            begin
              L_YY[2:0] <= OPC[7:5] ; 
            end
      default :
            begin
              L_YY[2:0] <= 3'bXXX ; 
            end
    endcase 
  end 

  always @(NFBH or ALUDAT_MOD or NEXT_REL_PC or L_YY)
  begin : set_high_addr
    // Program Counter High Byte Alternative Source Multiplexer
    case (NFBH)
      1'b0 :
            begin
              NEXT_PROGRAM_COUNT[10:8] <= L_YY[2:0] ; 
              NEXT_PROGRAM_COUNT[15:11] <= NEXT_REL_PC[15:11] ; 
            end
      1'b1 :
            begin
              NEXT_PROGRAM_COUNT[15:8] <= ALUDAT_MOD[7:0] ; 
            end
      default :
            begin
              NEXT_PROGRAM_COUNT[15:8] <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(ALUDAT or INTA)
  begin : set_int_vect_hi
    // Force upper address byte to zero during vector to interrupt ACALL.
    case (INTA)
      1'b1 :
            begin
              ALUDAT_MOD[7:0] <= 8'b00000000 ; 
            end
      1'b0 :
            begin
              ALUDAT_MOD <= ALUDAT ; 
            end
      default :
            begin
              ALUDAT_MOD <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 
  //*********************************************************************
endmodule