m3s007bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Conditional jump test subblock for m8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.008
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:04:57 1998
//
// Input file : m3s007bo.vhd
// Design name : m3s007bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s007bo.vhd
//Created on    :       8th October 1995
//Purpose       :       conditional jump test subblock for M8051
//Version       :       1.008
//Mod Date      :       2nd April 1998
//Mod History	:       1.008 _e suffix removed from entity names.
//                      1.007 STATDs 7-12 removed
//                      1.006 Sensivity List Revisions
//                      1.005 C_TRUE clocked at c2s4p1
//                      1.004-CTRU only clocked at end of CYC1
//                      1.003-changed CA inverted, CTRU delayed
//                      1.002-Calling file changed to m8051.vhd
//                      1.001(Original)
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//-------------------------------------------------
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s007bo (C_TRUE, ALUDAT, OPC, PSWDAT, CYC, STATD, BBIT, DIV2CK, NX1,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
RST);

  output C_TRUE;
  reg C_TRUE;
  input[7:0] ALUDAT;
  input[7:4] OPC;
  input[7:7] PSWDAT;
  input[2:2] CYC;
  input[3:3] STATD;
  input BBIT;
  input DIV2CK;
  input NX1;
  input RST;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg AA; 
  reg CA; 
  reg TMPCTRU; 

  always @(ALUDAT)
  begin : accumulator_zero
    // test for zero in the accumulator via ALU bus
    AA <= ALUDAT[0] | ALUDAT[1] | ALUDAT[2] | ALUDAT[3] | ALUDAT[4] | ALUDAT[
    5] | ALUDAT[6] | ALUDAT[7] ; 
  end 

  always @(OPC or PSWDAT or BBIT or AA)
  begin : misc3
    case (OPC[6:4])
      3'b000 :
            begin
              CA <= 1'b1 ; 
            end
      3'b001 :
            begin
              CA <= BBIT ; 
            end
      3'b010 :
            begin
              CA <= BBIT ; 
            end
      3'b011 :
            begin
              CA <= ~BBIT ; 
            end
      3'b100 :
            begin
              CA <= PSWDAT[7] ; 
            end
      3'b101 :
            begin
              CA <= ~PSWDAT[7] ; 
            end
      3'b110 :
            begin
              CA <= ~AA ; 
            end
      3'b111 :
            begin
              CA <= AA ; 
            end
      default :
            begin
              CA <= 1'bx ; 
            end
    endcase 
  end 

  always @(OPC or AA or CA)
  begin : misc4
    case (OPC[7])
      1'b0 :
            begin
              TMPCTRU <= CA ; 
            end
      1'b1 :
            begin
              TMPCTRU <= AA ; 
            end
      default :
            begin
              TMPCTRU <= 1'bx ; 
            end
    endcase 
  end 

  always @(posedge NX1 or posedge RST)
  begin : ctruout
    if (RST)
    begin
      C_TRUE <= 1'b0 ; 
    end
    else
    begin
      // Updates condition at the beginning of c2s4p1.  This output is used by
      // module m3s010bo at c2s5p1 and module m3s008 at c2s5p2 for jbc writes.
      if (CYC[2] & STATD[3] & ~DIV2CK)
      begin
        C_TRUE <= TMPCTRU ; 
      end 
    end 
  end 
  //*********************************************************************
endmodule