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📄 m3s029bo.v

📁 another 8051 core porocesssor vhdl source code
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//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      ////1 bit up counter(sync clear) for M8051//Copyright Mentor Graphics Corporation and Licensors 1998.  All rights reserved//v1.002//////////////////////////////////////////////////////////////////////////////////// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998// Thu Jul  9 22:06:02 1998//// Input file : m3s029bo.vhd// Design name : m3s029bo// Author : // Company : Mentor Graphics - Inventra//// Description : ////////////////////////////////////////////////////////////////////////////////////////*********************************************************************//%W% %G% SCCS Version Control//File	        :       m3s029bo.vhd//Created on    :       13th Dec 1995//Purpose       :       1 bit up counter with synchronous clear for M8051//Version       :       1.002//Mod Date      :       2nd April 1998//Mod History	:       1.002 _e suffix removed from entity names.//////////*********************************************************************//Hierarchy record      ://Called by             :m3s028bo.vhd//                      ://                      ://Calls to              :None//*********************************************************************//*********************************************************************//Entity Definition//*********************************************************************module m3s029bo (CO, Q, CI, CLEAR, COUNT_EN, NX1);//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      //  output CO;  reg CO;  output Q;  reg Q;  input CI;  input CLEAR;  input COUNT_EN;  input NX1;  //*********************************************************************  //*********************************************************************  //signal definition  //*********************************************************************  reg LQ;   reg NEXTQ;   always @(posedge NX1)  begin : countr    if (CLEAR)    begin      LQ <= 1'b0 ;     end    else if (COUNT_EN)    begin      LQ <= NEXTQ ;     end    end   always @(LQ or CI or CLEAR)  begin : set_nextq    NEXTQ <= (LQ | CI) & (~(CI & LQ)) & ~CLEAR ;   end   always @(LQ or CI or LQ)  begin : genout    Q <= LQ ;     CO <= CI & LQ ;   end   //*********************************************************************endmodule

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