m3s004bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Opcode Decoder for m8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.008
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:04:49 1998
//
// Input file : m3s004bo.vhd
// Design name : m3s004bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s004bo.vhd
//Created on    :       23th September 1995
//Purpose       :       opcode decoder for m8051
//Version       :       1.008
//Mod Date      :       2nd April 1998
//Mod History	:       1.008 _e suffix removed from entity names.
//                      1.007 PSW carry enable restricted.
//                      1.006 Name change for Verilog translation
//                      1.005 Sensitivity list revisions.
//                      1.004 ECN 878: CTRU and INTA removed from
//                            decoder.  RMW definition widened to
//                            include register instructions.
//                      1.003 ECN 842 -ORLC timing adjustment, 
//                            ECN      dummy address matching 
//                      1.002 Calling file name changed to m8051.vhd
//                      1.001 Original
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s004bo (ACCADD, PCADD, REGADD, MOVX, ALUC, CODAT, PSWC, TMPADD, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
SPC, ADDR_11BIT, JMPADPTR, LOGDI, GOCYC2, MULDIV, NMULAB, NDIVAB, DAA, CJNE,
RETI, EITHER_RET, RMW, JBC, IMMB3, IMMB4, OPC, DAAL, DAAH);

  output[9:0] ACCADD;
  wire[9:0] ACCADD;
  output[12:1] PCADD;
  wire[12:1] PCADD;
  output[10:0] REGADD;
  wire[10:0] REGADD;
  output[4:0] MOVX;
  reg[4:0] MOVX;
  output[17:0] ALUC;
  reg[17:0] ALUC;
  output[2:0] CODAT;
  reg[2:0] CODAT;
  output[2:0] PSWC;
  reg[2:0] PSWC;
  output[3:0] TMPADD;
  wire[3:0] TMPADD;
  output[3:0] SPC;
  reg[3:0] SPC;
  output ADDR_11BIT;
  wire ADDR_11BIT;
  output JMPADPTR;
  reg JMPADPTR;
  output LOGDI;
  wire LOGDI;
  output GOCYC2;
  reg GOCYC2;
  output MULDIV;
  wire MULDIV;
  output NMULAB;
  wire NMULAB;
  output NDIVAB;
  wire NDIVAB;
  output DAA;
  reg DAA;
  output CJNE;
  wire CJNE;
  output RETI;
  wire RETI;
  output EITHER_RET;
  wire EITHER_RET;
  output RMW;
  reg RMW;
  output JBC;
  wire JBC;
  output IMMB3;
  reg IMMB3;
  output IMMB4;
  reg IMMB4;
  input[7:0] OPC;
  input DAAL;
  input DAAH;

  //*********************************************************************
  //*********************************************************************
  //Component Definitions
  //*********************************************************************
  //Decode matrix
  //*********************************************************************
  //*********************************************************************
  //*********************************************************************
  //*********************************************************************
  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg AB; 
  reg AC; 
  reg INDIRECT_OPS; 
  reg MOVDAI; 
  reg AI; 
  reg AJ; 
  reg AK; 
  reg AM; 
  reg AN; 
  reg AU; 
  reg AV; 
  reg AW; 
  reg AX; 
  reg AY; 
  reg MOVRDA; 
  reg BA; 
  reg ARITH_OPS; 
  reg CARRY_OPS1; 
  reg CARRY_OPS2; 
  reg CARRY_OPS3; 
  wire LODEC_4TOF; 
  wire LDAA; 
  wire NLJMP; 
  wire NOP16; 
  wire LNMULAB; 
  wire LNDIVAB; 
  wire NCPLB; 
  wire NSETB; 
  wire NSETC; 
  wire NMOVCB; 
  wire NMOVBC; 
  wire NCLRB; 
  wire NCLRC; 
  wire NORLCN; 
  wire NORLCB; 
  wire NANLCN; 
  wire NANLCB; 
  wire LJBC; 
  wire NCPLC; 
  wire NMOVPC; 
  wire NINCDP; 
  wire NSWAPN; 
  wire LLOGDI; 
  reg LCJNE; 
  wire NDJNZD; 
  wire NDJNZR; 
  reg DJNZ; 
  wire PCLONG; 
  wire LO5TOF; 
  wire NLOGDA; 
  reg LMULDIV; 
  wire NCALL; 
  wire NLCALL; 
  reg LRET; 
  reg LRETI; 
  reg LEITHER_RET; 
  wire NPOP; 
  wire NPUSH; 
  wire[7:0] LLODEC; 
  wire[15:0] HIDEC; 
  wire[17:0] LALUC; 
  //*********************************************************************
  //Port Mapping
  //*********************************************************************
  //*********************************************************************
  m3s022bo U1 (.LODEC(LLODEC), .HIDEC(HIDEC), .OPC(OPC)); 
  //*********************************************************************
  m3s024bo U2 (.ALUC(LALUC), .LODEC_4TOF(LODEC_4TOF), .NDIVAB(LNDIVAB), .
  NDJNZD(NDJNZD), .NDJNZR(NDJNZR), .NMULAB(LNMULAB), .DAA(LDAA), .NLJMP(NLJMP),
  .NLCALL(NLCALL), .NOP16(NOP16), .NCPLB(NCPLB), .NSETB(NSETB), .NSETC(NSETC),
  .NORLCN(NORLCN), .NORLCB(NORLCB), .NMOVCB(NMOVCB), .NCLRB(NCLRB), .NCLRC(
  NCLRC), .NANLCN(NANLCN), .NANLCB(NANLCB), .JBC(LJBC), .NCPLC(NCPLC), .HIDEC(
  HIDEC), .LODEC(LLODEC[5:0]), .OPC(OPC[3:1]), .RET(LRET), .RETI(LRETI)); 
  //*********************************************************************
  m3s033bo U3 (.ACCADD(ACCADD), .NMOVPC(NMOVPC), .NINCDP(NINCDP), .NSWAPN(
  NSWAPN), .NMOVBC(NMOVBC), .LOGDI(LLOGDI), .HIDEC(HIDEC[14:0]), .LODEC(LLODEC),
  .OPC(OPC[7:3]), .LODEC_4TOF(LODEC_4TOF), .NOP16(NOP16), .MULDIV(LMULDIV),
  .INDXR(AI), .INDOP(INDIRECT_OPS), .NDIV(LNDIVAB), .NDJD(NDJNZD), .NDJR(NDJNZR),
  .NBEN(LALUC[17]), .CJNE(LCJNE), .NMUL(LNMULAB), .NMCB(NMOVCB)); 
  //*********************************************************************
  m3s032bo U4 (.TMPADD(TMPADD), .PCLONG(PCLONG), .LO5TOF(LO5TOF), .NLOGDA(
  NLOGDA), .HIDEC(HIDEC[11:2]), .LODEC(LLODEC[5:2]), .LODEC_4TOF(LODEC_4TOF),
  .ND16(NOP16), .MULDIV(LMULDIV), .NMPC(NMOVPC), .NLCA(NLCALL), .NLJM(NLJMP),
  .EITHER_RET(LEITHER_RET), .LOGDI(LLOGDI)); 
  //*********************************************************************
  m3s034bo U5 (.PCADD(PCADD), .HIDEC(HIDEC[15:0]), .LODEC(LLODEC[5:0]), .
  OPC(OPC[7:3]), .NLCALL(NLCALL), .BRET(LEITHER_RET), .PCL0(PCLONG), .DJNZ(
  DJNZ), .CJNE(LCJNE), .NIDP(NINCDP), .INDOP(INDIRECT_OPS), .LOGDI(LLOGDI),
  .NDJR(NDJNZR), .NDJD(NDJNZD)); 
  //*********************************************************************
  m3s035bo U6 (.REGADD(REGADD), .NCALL(NCALL), .NPOP(NPOP), .NPUSH(NPUSH),
  .HIDA(HIDEC[3:0]), .LODEC(LLODEC[2:0]), .OPC(OPC[4:3]), .HIDB(HIDEC[8:7]),
  .HIDC(HIDEC[13:10]), .HI15(HIDEC[15]), .L5TF(LO5TOF), .NLCA(NLCALL), .BRET(
  LEITHER_RET), .INDOP(INDIRECT_OPS), .INDXR(AI), .INDXW(AJ), .NLDA(NLOGDA),
  .LOGDI(LLOGDI), .NMBC(NMOVBC), .JBC(LJBC), .NBEN(LALUC[17]), .NSWA(NSWAPN),
  .NMCB(NMOVCB)); 

  always @(LNMULAB or HIDEC or LLODEC or NOP16 or NORLCB or NLJMP or NLCALL or 
   NMOVBC)
  begin : misc1
    AB <= LLODEC[1] | (LLODEC[0] & ~HIDEC[0]) ; 
    AC <= NOP16 & LNMULAB & NORLCB & NLJMP & NLCALL & NMOVBC ; 
  end 

  always @(HIDEC or LLODEC or OPC or LODEC_4TOF)
  begin : misc2
    LCJNE <= HIDEC[11] & LODEC_4TOF ; 
    LRET <= HIDEC[2] & LLODEC[2] ; 
    LRETI <= HIDEC[3] & LLODEC[2] ; 
    LEITHER_RET <= ~OPC[7] & ~OPC[6] & OPC[5] & LLODEC[2] ; 
    INDIRECT_OPS <= OPC[1] & OPC[2] & (~OPC[3]) ; 
    MOVDAI <= HIDEC[7] & LLODEC[5] ; 
    AI <= HIDEC[14] & (LLODEC[2] | LLODEC[3]) ; 
    AJ <= HIDEC[15] & (LLODEC[2] | LLODEC[3]) ; 
    AK <= (HIDEC[0] | HIDEC[1]) & LODEC_4TOF ; 
  end 

  always @(HIDEC or LLODEC or OPC or DAAL or DAAH or NDJNZR or NDJNZD or 
   LDAA or INDIRECT_OPS or LODEC_4TOF)
  begin : misc3
    DJNZ <= ~(NDJNZR & NDJNZD) ; 
    AM <= DAAL & LDAA ; 
    AN <= DAAH & LDAA ; 
    ARITH_OPS <= (HIDEC[2] | HIDEC[3] | HIDEC[9]) & LODEC_4TOF ; 
    CARRY_OPS1 <= HIDEC[11] & LODEC_4TOF ; 
    CARRY_OPS2 <= (HIDEC[1] | HIDEC[3]) & LLODEC[3] ; 
    AU <= HIDEC[14] & LLODEC[0] ; 
    AV <= HIDEC[15] & LLODEC[0] ; 
    AY <= (HIDEC[0] | HIDEC[1]) & LLODEC[5] ; 
    MOVRDA <= (OPC[3] | INDIRECT_OPS) & HIDEC[10] ; 
  end 

  always @(NORLCN or NANLCN or NORLCB or NANLCB or NMOVCB or NCPLC or NCLRC or 
   NSETC)
  begin : misc4
    CARRY_OPS3 <= ~(NORLCN & NANLCN & NORLCB & NANLCB & NMOVCB & NCPLC & 
    NCLRC & NSETC) ; 
  end 

  always @(AI or AJ or LJBC or NLOGDA or NMOVBC or NCPLB or NCLRB or NSETB or 
   NDJNZD or LLOGDI)
  begin : misc5
    AW <= (~AI) & (~AJ) ; 
    AX <= (~LJBC) & NLOGDA & NMOVBC & NCPLB & NCLRB & NSETB & NDJNZD & ~LLOGDI ;
      end 

  always @(LCJNE or LEITHER_RET or MOVRDA or MOVDAI or LLOGDI)
  begin : misc6
    BA <= LCJNE | LEITHER_RET | MOVRDA | MOVDAI | LLOGDI ; 
  end 

  always @(AB or AC or AI or AJ or AY or AX or BA or LDAA or NOP16 or LNDIVAB 
  or 
   LNMULAB or HIDEC or LLODEC or LLOGDI or LCJNE or PCLONG or NDJNZD or 
   OPC or DJNZ)
  begin : out1
    GOCYC2 <= AB | ~AC | AI | AJ | BA | HIDEC[8] | DJNZ ; 
    LMULDIV <= ~(LNDIVAB & LNMULAB) ; 
    DAA <= LDAA ; 
    RMW <= AY | ~AX | (OPC[4] & (HIDEC[0] | HIDEC[1] | HIDEC[13])) ; 
    IMMB3 <= (LLODEC[0] & (HIDEC[1] | HIDEC[2] | HIDEC[3] | HIDEC[9])) | ((
    HIDEC[7] | HIDEC[8]) & LLODEC[5]) | LCJNE | LLOGDI | PCLONG | ~NDJNZD ; 
    IMMB4 <= ~NOP16 ; 
    JMPADPTR <= HIDEC[7] & LLODEC[3] ; 
  end 

  always @(LALUC)
  begin : alucout
    ALUC <= LALUC ; 
  end 

  always @(AK or DJNZ or AM or AN)
  begin : codatout
    CODAT[0] <= AK | DJNZ ; 
    CODAT[1] <= AM ; 
    CODAT[2] <= AN ; 
  end 

  always @(AU or AV or AW or AJ or AI)
  begin : movx_control
    // External data access (MOVX) controller
    // 
    // Bit Definitions:
    // MOVX(0): Enable MOVX
    // MOVX(1): MOVX @Ri
    // MOVX(2): MOVX @DPTR
    // MOVX(3): MOVX WRITE
    // MOVX(4): MOVX READ
    // 
    MOVX[0] <= AU | AV | ~AW ; 
    MOVX[1] <= ~AW ; 
    MOVX[2] <= AU | AV ; 
    MOVX[3] <= AV | AJ ; 
    MOVX[4] <= AU | AI ; 
  end 

  always @(ARITH_OPS or LMULDIV or LDAA or CARRY_OPS1 or CARRY_OPS2 or CARRY_OPS3)
    begin : psw_control
    // Program Status Word Flag Controller
    // 
    // Bit Definitions:
    // PSWC(0): Enable Overflow Flag Load.
    // PSWC(1): Enable Half-Carry Flag Load,
    // PSWC(2): Enable Carry Flag Load,
    //
    PSWC[0] <= ARITH_OPS | LMULDIV ; 
    PSWC[1] <= ARITH_OPS ; 
    PSWC[2] <= ARITH_OPS | LMULDIV | LDAA | CARRY_OPS1 | CARRY_OPS2 | CARRY_OPS3 ;
      end 

  always @(LEITHER_RET or NPOP or NPUSH or NCALL)
  begin : spc_control
    // Stack Pointer Load, Increment and Decrement Controller
    //
    // Bit Definitions:
    // SPC(0): Stack Pointer Decrement
    // SPC(1): Stack Pointer Increment
    // SPC(2): Clock Stack Pointer in Machine Cycle 1 
    // SPC(3): Clock Stack Pointer in Machine Cycle 2 
    SPC[0] <= LEITHER_RET | ~NPOP ; 
    SPC[1] <= ~(NPUSH & NCALL) ; 
    SPC[2] <= ~NPUSH | ~NCALL | LEITHER_RET ; 
    SPC[3] <= ~NCALL | ~NPOP | LEITHER_RET ; 
  end 
  //*********************************************************************
  //localout:process(LLODEC,LLOGDI,LMULDIV, LJBC, LCJNE, LNMULAB, LNDIVAB, LRETI, LEITHER_RET)
  // Map local signal names to global names
  //begin
  assign ADDR_11BIT = LLODEC[1] ; 
  assign LOGDI = LLOGDI ; 
  assign MULDIV = LMULDIV ; 
  assign NMULAB = LNMULAB ; 
  assign NDIVAB = LNDIVAB ; 
  assign JBC = LJBC ; 
  assign CJNE = LCJNE ; 
  assign RETI = LRETI ; 
  assign EITHER_RET = LEITHER_RET ; 
  //end process localout;
  //*********************************************************************
endmodule