m3s025bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Opcode register sub-block for m8051
//Copyright Mentor Graphics Corpoarion and Licensors 1998.  All rights reserved
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:50 1998
//
// Input file : m3s025bo.vhd
// Design name : m3s025bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s025bo.vhd
//Created on    :       03th September 1995
//Purpose       :       Opcode latch sub block for m8051
//Version       :       1.005
//Mod Date      :       2nd April 1998
//Mod History	:       1.005 _e suffix removed from entity names.
//                      1.004 ECN 838-adjustment to opcode timing
//                      1.003 change for download mode
//                      1.002-Calling file changed to m8051.vhd
//                      1.001(Original)
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s025bo (OPC, OPLOAD, IROMD, STATD, PCON, CLEAR, RST, DIV2CK, NX1,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
INTA, LCYC, DLM);

  output[7:0] OPC;
  reg[7:0] OPC;
  output OPLOAD;
  reg OPLOAD;
  input[7:0] IROMD;
  input[1:1] STATD;
  input[0:0] PCON;
  input CLEAR;
  input RST;
  input DIV2CK;
  input NX1;
  input INTA;
  input LCYC;
  input DLM;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg L_OPLOAD; 
  reg[7:0] LOCALDAT; 

  always @(posedge NX1)
  begin : set_opccon
    L_OPLOAD <= LCYC & (~CLEAR) & (INTA | ~PCON[0]) & ~DLM ;  
  end 

  always @(posedge RST or posedge NX1)
  begin : dat_lat
    if (RST)
    begin
      OPC <= 8'b00000000 ; 
    end
    else
    begin
      if (L_OPLOAD & STATD[1] & DIV2CK)
      begin
        OPC <= LOCALDAT ; 
      end 
    end 
  end 

  always @(INTA or IROMD)
  begin : dir_con
    if (!INTA)
    begin
      LOCALDAT <= IROMD ; 
    end
    else
    begin
      LOCALDAT[0] <= 1'b0 ; 
      LOCALDAT[1] <= 1'b1 ; 
      LOCALDAT[2] <= 1'b0 ; 
      LOCALDAT[3] <= 1'b0 ; 
      LOCALDAT[4] <= 1'b1 ; 
      LOCALDAT[5] <= 1'b0 ; 
      LOCALDAT[6] <= 1'b0 ; 
      LOCALDAT[7] <= 1'b0 ; 
    end 
  end 

  always @(L_OPLOAD)
  begin : opcodeout
    OPLOAD <= L_OPLOAD ; 
  end 
  //*********************************************************************
endmodule