m3s034bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Program Counter control decoder for m8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//v1.006
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:06:14 1998
//
// Input file : m3s034bo.vhd
// Design name : m3s034bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s034bo.vhd
//Created on    :       11th September 1995
//Purpose       :       Program Counter control of m8051
//Version       :       1.006
//Mod Date      :       2nd April 1998
//Mod History	:       1.006 _e suffix removed from entity names.
//                      1.005 Sensitivity List Revisions.
//                      1.004 Comments Corrected.
//                      1.003 ECN 878: CTRU and INTA removed from
//                            decoder logic.
//			1.002 Changes to match dummy address cycles
//                      1.001 Original 
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s004bo.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s034bo (PCADD, HIDEC, LODEC, OPC, NLCALL, BRET, PCL0, DJNZ, CJNE,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
NIDP, INDOP, LOGDI, NDJR, NDJD);

  output[12:1] PCADD;
  reg[12:1] PCADD;
  input[15:0] HIDEC;
  input[5:0] LODEC;
  input[7:3] OPC;
  input NLCALL;
  input BRET;
  input PCL0;
  input DJNZ;
  input CJNE;
  input NIDP;
  input INDOP;
  input LOGDI;
  input NDJR;
  input NDJD;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg AA; 
  reg AB; 
  reg AD; 
  reg AE; 
  reg AG; 
  reg AH; 
  reg AI; 
  reg AK; 
  reg AL; 
  reg BB; 
  reg BC; 
  reg BD; 
  reg BE; 

  always @(HIDEC or LODEC or BRET or PCL0 or OPC or INDOP or CJNE or LOGDI)
  begin : misc1
    AA <= HIDEC[7] & LODEC[3] ; 
    AB <= BRET | PCL0 ; 
    AD <= LODEC[0] & (~OPC[7]) & (~HIDEC[0]) ; 
    AE <= HIDEC[9] & LODEC[0] ; 
    AG <= LODEC[1] | LODEC[5] ; 
    AH <= HIDEC[14] | HIDEC[15] | HIDEC[2] | HIDEC[3] | HIDEC[7] | HIDEC[
    8] | HIDEC[9] ; 
    AI <= INDOP | OPC[3] ; 
    AK <= (HIDEC[9] | HIDEC[11]) & OPC[7] & LODEC[4] ; 
    AL <= (~(HIDEC[0] | HIDEC[1] | OPC[7])) & LODEC[4] ; 
  end 

  always @(AA or AI or AH or DJNZ or CJNE or BRET or LODEC or HIDEC)
  begin : misc2
    //   BB <= AA or INTA or BRET;
    BB <= AA | BRET ; 
    BC <= LODEC[0] & (HIDEC[1] | HIDEC[2] | HIDEC[3] | HIDEC[9]) ; 
    BD <= AI & (HIDEC[7] | HIDEC[11]) ; 
    BE <= (~AH) & LODEC[2] ; 
  end 

  always @(AA or AB or AD or BB or HIDEC or LODEC or PCL0 or BRET or DJNZ or 
   CJNE)
  begin : pcout1
    PCADD[1] <= AA | BRET ; 
    //   PCADD(2) <= AA or INTA;
    PCADD[2] <= AA ; 
    PCADD[3] <= ~(BB | LODEC[1] | PCL0) ; 
    //   PCADD(4) <= AA or AB or INTA;
    PCADD[4] <= AA | AB ; 
    PCADD[5] <= AD | DJNZ | CJNE ; // conditional branches
    PCADD[12] <= HIDEC[8] & LODEC[0] ; // short jump (branch always)
  end 

  always @(AE or AG or AK or AL or BC or BD or BE or HIDEC or LODEC or NIDP or 
   LOGDI or NDJR or NDJD or CJNE or PCL0 or OPC or INDOP or NLCALL)
  begin : pcout2
    PCADD[6] <= (HIDEC[8] | HIDEC[9]) & LODEC[3] ; 
    PCADD[7] <= ~NIDP ; 
    PCADD[8] <= NIDP & (~AE) ; 
    PCADD[9] <= BC | AG | BE | BD | LOGDI | AK | AL ; 
    if (HIDEC[8:1] == 8'b00000000)
    begin
      PCADD[10] <= CJNE | (~NLCALL) | (~NDJD) | ~NDJR ; 
    end
    else
    begin
      PCADD[10] <= LODEC[0] | CJNE | (~NDJD) | ~NDJR | ~NLCALL ; 
    end 
    PCADD[11] <= (OPC[3] & (HIDEC[8] | HIDEC[10])) | (LODEC[0] & (HIDEC[9]
    | HIDEC[10] | HIDEC[11] | HIDEC[12] | HIDEC[13])) | (LODEC[2] & (HIDEC[7]
    | HIDEC[8] | HIDEC[9])) | (LODEC[5] & (HIDEC[7] | HIDEC[8])) | (INDOP & (
    HIDEC[8] | HIDEC[10])) | LOGDI ; 
  end 
  //*********************************************************************
endmodule