m3s035bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Register File Control Decoder for M8051
//Copyright Mentor Graphics Corporation and Licensors 1999. All rights reserved.
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_21 Jan. 15, 1999
// Tue Mar 30 16:49:56 1999
//
// Input file : m3s035bo.vhd
// Design name : m3s035bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s035bo.vhd
//Created on    :       4 Jan 1996
//Purpose       :       M8051 Register File Control Decoder
//Version       :       1.005
//Mod Date      :       22nd January 1999
//Mod History	:	1.005 Redundant ESFR read cycles masked out during jumps
//                            Intermediate terms removed.
//                      1.004 _e suffix removed from entity names.
//                      1.003 Comments added for REGADD(5-10)
//                      1.002 ECN 878: CTRU removed from decoder
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s004bo.vhd
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s035bo (REGADD, NCALL, NPOP, NPUSH, HIDA, LODEC, OPC, HIDB, HIDC,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
HI15, L5TF, NLCA, BRET, INDOP, INDXR, INDXW, NLDA, LOGDI, NMBC, JBC, NBEN,
NSWA, NMCB);

  output[10:0] REGADD;
  reg[10:0] REGADD;
  output NCALL;
  reg NCALL;
  output NPOP;
  reg NPOP;
  output NPUSH;
  reg NPUSH;
  input[3:0] HIDA;
  input[2:0] LODEC;
  input[4:3] OPC;
  input[8:7] HIDB;
  input[13:10] HIDC;
  input HI15;
  input L5TF;
  input NLCA;
  input BRET;
  input INDOP;
  input INDXR;
  input INDXW;
  input NLDA;
  input LOGDI;
  input NMBC;
  input JBC;
  input NBEN;
  input NSWA;
  input NMCB;

  //*********************************************************************
  reg AA; 
  reg AB; 
  reg AC; 
  reg AD; 
  reg AE; 
  reg AF; 
  reg AG; 
  reg AH; 
  reg AI; 
  reg AJ; 
  reg AK; 
  reg AL; 
  reg AM; 
  reg AO; 
  reg AP; 
  reg CALLRETS; 

  always @(HIDA or HIDB or HIDC or HI15 or JBC or L5TF or LODEC or INDOP or 
   INDXR or INDXW or OPC or NLCA)
  begin : misc1
    // Generate intermediate signal prior to producing regadd(0,1,2,3,4)
    AA <= HIDB[7] & L5TF ; 
    AB <= (LODEC[1] & OPC[4]) | ~NLCA ; 
    AC <= (HIDC[12] | HIDC[13]) & LODEC[0] ; 
    AD <= L5TF & HIDB[8] ; 
    AE <= (INDOP | OPC[3]) & HIDC[10] ; 
    AF <= OPC[3] & ~HIDC[10] ; 
    AG <= HIDC[13] & LODEC[0] ; 
    AH <= (~HIDC[10] & INDOP) | INDXR | INDXW ; 
    AI <= (LODEC[1] & ~OPC[4]) | (LODEC[2] & HIDA[0]) ; 
    //generate intermediate signals prior to producing regadd(5,6,7,8,9,10)
    AJ <= HIDC[10] & OPC[3] ; 
    AK <= HIDC[12] & LODEC[0] ; 
    AL <= INDOP & HIDC[10] ; 
    AM <= (HIDA[0] | HIDA[1] | HIDB[7] | HIDB[8] | HIDC[10] | HIDC[12] | 
    HIDC[13] | HI15) & L5TF ; 
    AO <= (HIDC[11] | HIDC[12] | HIDC[13]) & LODEC[2] ; 
    AP <= (HIDA[2] | HIDA[3] | HIDC[10] | HIDC[11]) & LODEC[0] ; 
  end 

  always @(AA or AB or AC or AD or AE or AF or AG or AH or AI or NSWA or 
   CALLRETS)
  begin : regout1
    REGADD[0] <= AA | AB ; 
    REGADD[1] <= ~NSWA | AB ; 
    REGADD[2] <= AC | AD | AE | CALLRETS ; 
    REGADD[3] <= AF | AH | AI ; 
    REGADD[4] <= AG | CALLRETS | AH | AI ; 
  end 

  always @(AB or AC or AI or AJ or AL or AK or AM or AO or AP or INDXR or 
   INDXW or INDOP or NLDA or LOGDI or NMBC or NMCB or NBEN or CALLRETS or 
   JBC)
  begin : regout2
    REGADD[5] <= AI | AJ | AL ; 
    REGADD[6] <= AI | AK | AL | CALLRETS ; 
    REGADD[7] <= INDXR | INDXW | INDOP ; 
    REGADD[8] <= AM | AB | AC | ~NLDA | LOGDI | ~NMBC | JBC | AO ; 
    REGADD[9] <= AB ; 
    REGADD[10] <= AP | ~NBEN | ~NMCB ; 
  end 

  always @(AB or AC or AG or AK or BRET)
  begin : miscout
    NCALL <= ~AB ; 
    NPOP <= ~AG ; 
    CALLRETS <= BRET | AB ; 
    NPUSH <= ~AK ; 
  end 
  //*********************************************************************
endmodule