m3s008bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// RAM and Special Function Register Controller for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v2.001
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:01 1998
//
// Input file : m3s008bo.vhd
// Design name : m3s008bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s008bo.vhd
//Created on    :       14th March 1997
//Purpose       :       RAM and SFR controller for M8051
//Version       :       2.001
//Mod Date      :       2nd April 1998 
//Mod History	:       2.001 _e suffix removed from entity names.
//                      2.000 Re-written for SFR Expansion Capability,
//                            FA and FO outputs registered,
//                            redundancy removed from SFR control.
//                      1.006 Stack read address setup time advanced for
//                            second half of RET instructions.
//                            Direct register bank address generation
//                            simplified.
//                            Bit mode address generator moved.
//                            Sensitivity list revisions.
//			1.005 ECN 878: C_TRUE controls JBC writeback
//                            directly. Direct register bank write backs
//                            now take place at s4p2 in cycle 2.
//                            Indirect addresses stored in separate
//                            register: Ind_Addr.  Data write time
//                            restored to end of S6P2.
//                      1.004 Change to define FA during reset
//                      1.003 Timing correction 
//                      1.002 Calling file name changed to m8051.vhd
//                      1.001 Original
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :m3s009bo.vhd
//                      :m3s039bo.vhd
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s008bo (WEP, NFOE, NFWE, NSFROE, NSFRWE, BIT_POSN, RAMDI, FA, RDAT,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
SFRW, JBC, EITHER_RET, C_TRUE, NESFR, CLEAR, LCYC, RESINT, DIV2CK, NX1, RST,
ALUDAT, IMMDAT, SFRDAT, SP, IROMD, FI, CYC, OPC, PSWDAT, REGADD, STATD, STACK_DATA);

  output WEP;
  wire WEP;
  output NFOE;
  reg NFOE;
  output NFWE;
  reg NFWE;
  output NSFROE;
  reg NSFROE;
  output NSFRWE;
  reg NSFRWE;
  output[2:0] BIT_POSN;
  reg[2:0] BIT_POSN;
  output[7:0] RAMDI;
  reg[7:0] RAMDI;
  output[7:0] FA;
  reg[7:0] FA;
  output[7:0] RDAT;
  reg[7:0] RDAT;
  output[21:0] SFRW;
  wire[21:0] SFRW;
  input JBC;
  input EITHER_RET;
  input C_TRUE;
  input NESFR;
  input CLEAR;
  input LCYC;
  input RESINT;
  input DIV2CK;
  input NX1;
  input RST;
  input[7:0] ALUDAT;
  input[7:0] IMMDAT;
  input[7:0] SFRDAT;
  input[7:0] SP;
  input[7:0] IROMD;
  input[7:0] FI;
  input[2:1] CYC;
  input[3:0] OPC;
  input[4:3] PSWDAT;
  input[10:0] REGADD;
  input[6:1] STATD;
  input[15:0] STACK_DATA;

  //*********************************************************************
  //*********************************************************************
  // Component Definitions
  //*********************************************************************
  //Register mux
  //*********************************************************************
  //SFR write strobe decoder sub-module
  //*********************************************************************
  //*********************************************************************
  //signal definition
  //*********************************************************************
  reg FA_EN; 
  reg SFR_LOAD; 
  reg SEL_SFR_NRAM; 
  reg JBC_FAILED; 
  reg FOE; 
  reg FWE; 
  reg SFROE; 
  reg SFRWE; 
  reg SEL_DIRADDR; 
  reg SEL_STACKPTR; 
  reg SEL_INDADDR; 
  reg SEL_REGBANK; 
  reg[7:0] L_FA; 
  reg[7:0] L_RDAT; 
  wire[7:0] ASYNC_RAMDI; 
  reg[7:0] INDIRECT_ADDR; 
  reg[7:0] DIRECT_ADDR; 
  reg[7:0] REG_BANK_ADDR; 
  reg[7:0] BIT_MODE_ADDR; 
  reg[7:0] NEXT_FA; 
  //*********************************************************************
  //*********************************************************************
  //port mapping
  //*********************************************************************
  //*********************************************************************
  m3s009bo U1 (.RAMDI(ASYNC_RAMDI), .STACK_DATA(STACK_DATA), .IMMDAT(IMMDAT),
  .ALUDAT(ALUDAT), .REGADD(REGADD[1:0]), .CYC(CYC[2:2]), .STATD(STATD[5:5]),
  .RDAT(L_RDAT[7:4]), .DIV2CK(DIV2CK), .NX1(NX1), .RST(RST)); 
  //*********************************************************************
  m3s039bo U2 (.SFRW(SFRW), .WEP(WEP), .FA(L_FA[6:0]), .SFR_LOAD(SFR_LOAD),
  .SFRWE(SFRWE)); 

  always @(JBC or C_TRUE)
  begin : jbc_mask
    // prevent register write back in JBC instructions if condition not met
    JBC_FAILED <= JBC & ~(C_TRUE) ; 
  end 

  always @(CYC or REGADD or STATD or CLEAR or EITHER_RET)
  begin : gen1
    // Data memory address set at C1S2P1 for indirection register read.
    // Otherwise data memory address generally set at the end of S4P1 only, 
    // except that during a RET instruction the second stack read takes
    // place at C2S1P1.
    FA_EN <= ((CYC[1] & STATD[2]) | (CYC[1] & STATD[4]) | (CYC[2] & STATD[
    1] & EITHER_RET) | (CYC[2] & STATD[4] & REGADD[2])) & ~CLEAR ; 
  end 

  always @(IMMDAT or IROMD or CYC)
  begin : mux_direct_addr
    if (CYC[2])
    begin
      DIRECT_ADDR <= IMMDAT ; 
    end
    else
    begin
      DIRECT_ADDR <= IROMD ; 
    end 
  end 

  always @(posedge NX1 or posedge RST)
  begin : set_addr_mode
    if (RST)
    begin
      SEL_DIRADDR <= 1'b1 ; 
      SEL_REGBANK <= 1'b0 ; 
      SEL_INDADDR <= 1'b0 ; 
      SEL_STACKPTR <= 1'b0 ; 
    end
    else
    begin
      if (CYC[1] & STATD[1] & DIV2CK)
      begin
        // always start an instruction with a register bank read
        SEL_DIRADDR <= 1'b0 ; 
        SEL_REGBANK <= 1'b1 ; 
        SEL_INDADDR <= 1'b0 ; 
        SEL_STACKPTR <= 1'b0 ; 
      end
      else if (STATD[3] & DIV2CK)
      begin
        if (CYC[1] | ~REGADD[2])
        begin
          SEL_DIRADDR <= ~REGADD[3] & ~REGADD[4] ; 
          SEL_REGBANK <= REGADD[3] & ~REGADD[4] ; 
          SEL_STACKPTR <= ~REGADD[3] & REGADD[4] ; 
          SEL_INDADDR <= REGADD[3] & REGADD[4] ; 
        end
        else
        begin
          SEL_DIRADDR <= ~REGADD[5] & ~REGADD[6] ; 
          SEL_REGBANK <= REGADD[5] & ~REGADD[6] ; 
          SEL_STACKPTR <= ~REGADD[5] & REGADD[6] ; 
          SEL_INDADDR <= REGADD[5] & REGADD[6] ; 
        end 
      end 
    end 
  end 

  always @(DIRECT_ADDR or REG_BANK_ADDR or INDIRECT_ADDR or SP or BIT_MODE_ADDR 
  or 
   SEL_REGBANK or SEL_INDADDR or SEL_STACKPTR or SEL_DIRADDR or REGADD)
  begin : select_next_FA
    // Main register address multiplexer
    // This 5:1 MUX selects addressing mode and address source.
    // REGADD(10) is decoded from the opcode to select bit addressing mode.
    // SEL_REGBANK, SEL_INDADDR, SEL_STACKPTR and REGADD(10) are mutually
    // exclusive.
    NEXT_FA <= 8'b00000000 ; 
    begin : xhdl_1
      integer I;
      for(I = 0; I <= 7; I = I + 1)
      begin
        NEXT_FA[I] <= (SEL_DIRADDR & ~REGADD[10] & DIRECT_ADDR[I]) | (SEL_DIRADDR &
        REGADD[10] & BIT_MODE_ADDR[I]) | (SEL_REGBANK & REG_BANK_ADDR[I]) | (SEL_STACKPTR &
        SP[I]) | (SEL_INDADDR & INDIRECT_ADDR[I]) ; 
      end
    end 
  end 

  always @(posedge NX1 or posedge RST)
  begin : load_FA
    if (RST)
    begin
      L_FA <= 8'b00000000 ; 
      BIT_POSN <= 3'b000 ; 
      SEL_SFR_NRAM <= 1'b0 ; 
      SFR_LOAD <= 1'b0 ; 
    end
    else
    begin
      // Load register containing address for data memory or SFR accesses.
      // SFRs can be selected as source or destination for direct memory
      // accesses to addresses greater than 80h.
      if (FA_EN & DIV2CK)
      begin
        L_FA <= NEXT_FA ; 
        BIT_POSN <= DIRECT_ADDR[2:0] ; 
        SEL_SFR_NRAM <= NEXT_FA[7] & SEL_DIRADDR ; 
        SFR_LOAD <= NEXT_FA[7] & SEL_DIRADDR & ~RESINT & REGADD[8] ; 
      end 
    end 
  end 

  always @(posedge NX1 or posedge RST)
  begin : file_control
    if (RST)
    begin
      FOE <= 1'b0 ; 
      FWE <= 1'b0 ; 
      SFRWE <= 1'b0 ; 
      SFROE <= 1'b0 ; 
      RAMDI <= 8'b00000000 ; 
    end
    else
    begin
      // Data memory output enable: this on goes inactive during a data memory
      // write cycle, i.e. from one clock before FWE to one clock after FWE.
      // Data memory writes take place at end of S6P2, i.e. on the falling
      // edge of FWE.
      // always turn off RAM and SFR reads for state 6 of last cycle
      if (CYC[1] & STATD[1])
      begin
        // Always enable data memory at the beginning of a new
        // instruction in order to load indirect address register.
        FOE <= 1'b1 ; 
        SFROE <= 1'b0 ; 
      end
      else if (STATD[4] & DIV2CK & ~RESINT)
      begin
        // Select data memory or SFR as source of register data.
        FOE <= ~(NEXT_FA[7] & SEL_DIRADDR) ; 
        SFROE <= NEXT_FA[7] & SEL_DIRADDR ; 
      end
      else if (STATD[5] & ~DIV2CK & ~RESINT)
      begin
        // Memory is not read after S5 if a register is to be loaded
        // and is not read at all during CALLs (REGADD(9) = 1).
        FOE <= ~SEL_SFR_NRAM & ~((LCYC & REGADD[8]) | REGADD[9]) ; 
        SFROE <= SEL_SFR_NRAM & ~((LCYC & REGADD[8]) | REGADD[9]) ; 
      end 
      if (STATD[6])
      begin
        FWE <= DIV2CK & ~RESINT & ((LCYC & REGADD[8]) | REGADD[9]) & ~SEL_SFR_NRAM &
        ~JBC_FAILED ; 
        SFRWE <= DIV2CK & ~RESINT & LCYC & REGADD[8] & SEL_SFR_NRAM & ~JBC_FAILED ;
                RAMDI <= ASYNC_RAMDI ; 
      end 
    end 
  end 

  always @(OPC or PSWDAT)
  begin : reg_addr_gen
    // Generate register bank address from instruction byte.
    // The register bank address is derived from the opcode register
    // directly.  Indirect address generation must take place in the first
    // half of cycle 1 and may only source from R0 or R1. 
    REG_BANK_ADDR[0] <= OPC[0] ; 
    REG_BANK_ADDR[1] <= OPC[1] & OPC[3] ; 
    REG_BANK_ADDR[2] <= OPC[2] & OPC[3] ; 
    REG_BANK_ADDR[4:3] <= PSWDAT[4:3] ; 
    REG_BANK_ADDR[7:5] <= 3'b000 ; 
  end 

  always @(DIRECT_ADDR)
  begin : bit_addr_gen
    if (!(DIRECT_ADDR[7]))
    begin
      BIT_MODE_ADDR[3:0] <= DIRECT_ADDR[6:3] ; 
      BIT_MODE_ADDR[4] <= 1'b0 ; 
      BIT_MODE_ADDR[5] <= 1'b1 ; 
      BIT_MODE_ADDR[6] <= 1'b0 ; 
    end
    else
    begin
      BIT_MODE_ADDR[2:0] <= 3'b000 ; 
      BIT_MODE_ADDR[6:3] <= DIRECT_ADDR[6:3] ; 
    end 
    BIT_MODE_ADDR[7] <= DIRECT_ADDR[7] ; 
  end 

  always @(posedge NX1 or posedge RST)
  begin : load_ind_addr
    if (RST)
    begin
      INDIRECT_ADDR <= 8'b00000000 ; 
    end
    else
    begin
      // Load indirect address register with data read from register bank. 
      // This always takes place at the start of c1s4p1.
      if (CYC[1] & STATD[3] & ~DIV2CK)
      begin
        INDIRECT_ADDR <= FI ; 
      end 
    end 
  end 

  always @(SFRDAT or NESFR or FI or SEL_SFR_NRAM)
  begin : muxrdat
    if (SEL_SFR_NRAM & NESFR)
    begin
      L_RDAT <= SFRDAT ; 
    end
    else
    begin
      L_RDAT <= FI ; 
    end 
  end 

  always @(L_FA or L_RDAT or FOE or FWE or SFROE or SFRWE)
  begin : localout
    // Export local signals with their global names
    FA <= L_FA ; 
    RDAT <= L_RDAT ; 
    NFOE <= ~FOE ; 
    NFWE <= ~FWE ; 
    NSFROE <= ~SFROE ; 
    NSFRWE <= ~SFRWE ; 
  end 
  //********************************************************************* 
endmodule