m3s019bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Interrupt Controller for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:35 1998
//
// Input file : m3s019bo.vhd
// Design name : m3s019bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s019bo.vhd
//Created on    :       13th Dec 1995
//Purpose       :       Interrupt control and priority regs etc for M8051
//Version       :       1.005
//Mod Date      :       2nd April 1998
//Mod History	:       1.005 _e suffix removed from entity names.
//                      1.004 Name changes and sensitivity list
//                            revisions.
//                      1.003 Idle Mode Power Saving
//			1.002 Calling file name changed to m8051.vhd
//                      1.001 Original
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s019bo (INTA, IE, IP, VECTOR_ADDR, IACK, RITI, WEP, RETI, LCYC, 
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
T_EN, S_EN, DIV2CK, CLEAR, RST, NX1, NX2, STATD, CYC, TCON, RAMDI, SFRW);

  output INTA;
  reg INTA;
  output[7:0] IE;
  reg[7:0] IE;
  output[7:0] IP;
  reg[7:0] IP;
  output[4:1] VECTOR_ADDR;
  reg[4:1] VECTOR_ADDR;
  output[3:0] IACK;
  reg[3:0] IACK;
  input RITI;
  input WEP;
  input RETI;
  input LCYC;
  input T_EN;
  input S_EN;
  input DIV2CK;
  input CLEAR;
  input RST;
  input NX1;
  input NX2;
  input[1:1] STATD;
  input[2:2] CYC;
  input[7:1] TCON;
  input[7:0] RAMDI;
  input[13:12] SFRW;

  //*********************************************************************
  //*********************************************************************
  //signal definition
  //*********************************************************************
  reg IP0; 
  reg IP1; 
  reg L_INTA; 
  reg PRA; 
  reg PRB; 
  reg PRC; 
  reg PRD; 
  reg PRE; 
  reg INT_EN; 
  reg AA; 
  reg AB; 
  reg AC; 
  reg AD; 
  reg AE; 
  reg AF; 
  reg AG; 
  reg AH; 
  reg AI; 
  reg AJ; 
  reg AK; 
  reg AL; 
  reg BA; 
  reg BB; 
  reg[7:0] L_IE; 
  reg[7:0] L_IP; 
  reg[4:0] ILA; 
  reg[4:0] ILB; 
  reg[4:0] ILL; 
  reg[4:0] LAT_ILA; 
  reg[4:0] LAT_ILB; 

  always @(L_IE or STATD or PRA or PRB or PRC or PRD or PRE or ILA or ILB or 
   ILL or CYC or L_INTA)
  begin : misc1
    AA <= L_IE[0] & L_IE[7] & PRA ; 
    AB <= L_IE[1] & L_IE[7] & PRB ; 
    AC <= L_IE[2] & L_IE[7] & PRC ; 
    AD <= L_IE[3] & L_IE[7] & PRD ; 
    AE <= L_IE[4] & L_IE[7] & PRE ; 
    AF <= ILA[0] | ILA[1] | ILA[2] | ILA[3] | ILA[4] ; 
    AG <= ILB[0] | ILB[1] | ILB[2] | ILB[3] | ILB[4] ; 
    AH <= ILL[1] & ~ILL[0] ; 
    AI <= ILL[2] & ~(ILL[1] | ILL[0]) ; 
    AJ <= ILL[3] & ~(ILL[2] | ILL[1] | ILL[0]) ; 
    AK <= ILL[4] & ~(ILL[3] | ILL[2] | ILL[1] | ILL[0]) ; 
    AL <= STATD[1] & CYC[2] & L_INTA ; 
  end 

  always @(WEP or RETI or IP0 or IP1 or AF or AG)
  begin : misc2
    BA <= WEP | RETI | IP1 | ~AG ; 
    BB <= WEP | RETI | IP1 | IP0 | AG | ~AF ; 
  end 

  always @(posedge NX1 or posedge RST)
  begin : priorlevelsel
    if (RST)
    begin
      PRA <= 1'b0 ; 
      PRB <= 1'b0 ; 
      PRC <= 1'b0 ; 
      PRD <= 1'b0 ; 
      PRE <= 1'b0 ; 
    end
    else
    begin
      if (((~DIV2CK) & S_EN))
      begin
        PRA <= TCON[1] ; 
        PRB <= TCON[5] ; 
        PRC <= TCON[3] ; 
        PRD <= TCON[7] ; 
        PRE <= RITI ; 
      end 
    end 
  end 

  always @(L_IP or AA or AB or AC or AD or AE)
  begin : intprior_0
    ILA[0] <= AA & ~L_IP[0] ; 
    ILA[1] <= AB & ~L_IP[1] ; 
    ILA[2] <= AC & ~L_IP[2] ; 
    ILA[3] <= AD & ~L_IP[3] ; 
    ILA[4] <= AE & ~L_IP[4] ; 
  end 

  always @(L_IP or AA or AB or AC or AD or AE)
  begin : intprior_1
    ILB[0] <= AA & L_IP[0] ; 
    ILB[1] <= AB & L_IP[1] ; 
    ILB[2] <= AC & L_IP[2] ; 
    ILB[3] <= AD & L_IP[3] ; 
    ILB[4] <= AE & L_IP[4] ; 
  end 

  always @(posedge NX1 or posedge RST)
  begin : setint_en
    if (RST)
    begin
      INT_EN <= 1'b0 ; 
    end
    else
    begin
      if (DIV2CK)
      begin
        INT_EN <= T_EN ; 
      end 
    end 
  end 

  always @(posedge NX1)
  begin : setip1
    if (CLEAR)
    begin
      IP1 <= 1'b0 ; 
    end
    else if (INT_EN & DIV2CK)
    begin
      if ((RETI | ~IP1))
      begin
        IP1 <= LCYC & ~BA ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : setip0
    if (CLEAR)
    begin
      IP0 <= 1'b0 ; 
    end
    else if (INT_EN & DIV2CK)
    begin
      if (((RETI & (~LCYC) & ~IP1) | ~(IP0 | IP1)))
      begin
        IP0 <= LCYC & ~BB ; 
      end 
    end  
  end 

  always @(posedge NX1)
  begin : setlilx
    if (INT_EN & LCYC & DIV2CK)
    begin
      LAT_ILA <= ILA ; 
      LAT_ILB <= ILB ; 
    end  
  end 

  always @(LAT_ILA or LAT_ILB or IP1)
  begin : setill
    if (!IP1)
    begin
      ILL <= LAT_ILA ; 
    end
    else
    begin
      ILL <= LAT_ILB ; 
    end 
  end 

  always @(posedge NX2)
  begin : setie
    if (CLEAR)
    begin
      L_IE <= 8'b00000000 ; 
    end
    else if ((SFRW[12]))
    begin
      L_IE <= RAMDI ; 
    end  
  end 

  always @(posedge NX2)
  begin : setip
    if (CLEAR)
    begin
      L_IP <= 8'b00000000 ; 
    end
    else if ((SFRW[13]))
    begin
      L_IP <= RAMDI ; 
    end  
  end 

  always @(L_IE or L_IP or L_INTA)
  begin : localout
    IE <= L_IE ; 
    IP <= L_IP ; 
    INTA <= L_INTA ; 
  end 

  always @(posedge NX1 or posedge RST)
  begin : setinta
    if (RST)
    begin
      L_INTA <= 1'b0 ; 
    end
    else
    begin
      if (CLEAR)
      begin
        L_INTA <= 1'b0 ; 
      end
      else if ((INT_EN & DIV2CK & LCYC))
      begin
        L_INTA <= ~(BA & BB) ; 
      end 
    end 
  end 

  always @(CLEAR or AL or ILL or AH or AI or AJ)
  begin : hardintack
    if (CLEAR)
    begin
      IACK <= 4'b0000 ; 
    end
    else if (!AL)
    begin
      IACK <= 4'b1111 ; 
    end
    else
    begin
      IACK[0] <= ~ILL[0] ; 
      IACK[1] <= ~AH ; 
      IACK[2] <= ~AI ; 
      IACK[3] <= ~AJ ; 
    end 
  end 

  always @(AH or AI or AJ or AK or IP0 or IP1)
  begin : intvect
    VECTOR_ADDR[1] <= IP0 | IP1 ; 
    VECTOR_ADDR[2] <= AH | AJ ; 
    VECTOR_ADDR[3] <= AI | AJ ; 
    VECTOR_ADDR[4] <= AK ; 
  end 
  //*********************************************************************
endmodule