m3s001bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Clock Generator and State Machine for M8051
//(c) Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//v1.009
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:04:35 1998
//
// Input file : m3s001bo.vhd
// Design name : m3s001bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s001bo.vhd
//Created on    :       8th September 1995
//Purpose       :       Clock Generator of m8051
//Version       :       1.009
//Mod Date      :       2nd April 1998
//Mod History	:       1.009 _e suffix removed from entity names.
//                      1.008 States 7-12 removed.
//                      1.007 GOCYC3 renamed MULDIV to remove redundancy
//                      1.006 DIV2CK2 revision to continue support for
//                            non-powersaving implementations.
//                      1.005 Idle Mode Power Saving
//			1.004 ECN 823- clash of STD signal naming with
//                                     code coverage tool 
//                      1.003 ECN 838- adjustment to OPC timing
//                      1.002 ECN 817-PCON.0(Idle) timing
//                      1.001(Original)
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s001bo (STATD, CYC, LCYC, DIV2CK1, DIV2CK2, S_EN, T_EN, STATE12,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
RST, GOCYC2, MULDIV, NX1, NX2, PCON);

  output[6:1] STATD;
  reg[6:1] STATD;
  output[3:1] CYC;
  reg[3:1] CYC;
  output LCYC;
  reg LCYC;
  output DIV2CK1;
  reg DIV2CK1;
  output DIV2CK2;
  reg DIV2CK2;
  output S_EN;
  reg S_EN;
  output T_EN;
  reg T_EN;
  output STATE12;
  reg STATE12;
  input RST;
  input GOCYC2;
  input MULDIV;
  input NX1;
  input NX2;
  input[0:0] PCON;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg LDV2CK1; 
  reg LDV2CK2; 
  reg SMA; 
  reg SMB; 
  reg SMC; 
  reg SMD; 
  reg SME; 
  reg SMF; 
  reg Q4; 
  reg Q5; 
  reg LCYCI; 

  always @(posedge NX1 or posedge RST)
  begin : lckdiv
    if (RST)
    begin
      LDV2CK1 <= 1'b0 ; 
      LDV2CK2 <= 1'b0 ; 
    end
    else
    begin
      LDV2CK1 <= ~(LDV2CK1) ; 
      LDV2CK2 <= ~(LDV2CK1) | PCON[0] ; // remains high in idle
    end 
  end 

  always @(LDV2CK1 or LDV2CK2)
  begin : internck
    DIV2CK1 <= LDV2CK1 ; 
    DIV2CK2 <= LDV2CK2 ; 
  end 

  always @(posedge RST or posedge NX1)
  begin : st_mhc
    if (RST)
    begin
      SMA <= 1'b0 ; 
      SMB <= 1'b0 ; 
      SMC <= 1'b0 ; 
      SMD <= 1'b0 ; 
      SME <= 1'b0 ; 
      SMF <= 1'b0 ; 
      S_EN <= 1'b0 ; 
    end
    else
    begin
      // A six-position ring counter is the state generator
      // The state counter continues to count during idle mode.
      if (!LDV2CK1)
      begin
        SMF <= ~(SMF | SMA | SMB | SMC | SMD) ; 
        SME <= SMD ; 
        SMD <= SMC ; 
        SMC <= SMB ; 
        SMB <= SMA ; 
        SMA <= SMF ; 
      end 
      S_EN <= SME ; 
    end 
  end 

  always @(posedge RST or posedge NX1)
  begin : state6_out
    if (RST)
    begin
      STATE12 <= 1'b0 ; 
    end
    else
    begin
      //used for UART, not stopped in idle.
      if (LDV2CK1)
      begin
        STATE12 <= SMF ; 
      end 
    end 
  end 

  always @(posedge RST or posedge NX2)
  begin : st_out
    if (RST)
    begin
      STATD <= 6'b000000 ; 
    end
    else
    begin
      if (!(PCON[0]))
      begin
        if (!LDV2CK2)
        begin
          STATD[1] <= SMF ; 
          STATD[2] <= SMA ; 
          STATD[3] <= SMB ; 
          STATD[4] <= SMC ; 
          STATD[5] <= SMD ; 
          STATD[6] <= SME ; 
        end 
      end 
    end 
  end 

  always @(posedge NX2 or posedge RST)
  begin : lcyctimer
    if (RST)
    begin
      LCYC <= 1'b1 ; 
    end
    else
    begin
      if (SMA & ~LDV2CK2)
      begin
        LCYC <= LCYCI ; 
      end 
    end 
  end 

  always @(SMB or SME or Q4 or Q5 or GOCYC2 or MULDIV or LDV2CK1)
  begin : misc_out
    CYC[3] <= Q4 & Q5 ; 
    CYC[2] <= Q4 & (~Q5) ; 
    CYC[1] <= ~(Q4 | Q5) ; 
    LCYCI <= (Q4 & Q5 & MULDIV) | (Q4 & ~MULDIV) | (~GOCYC2) ; 
    T_EN <= (SMB & ~LDV2CK1) | (SME & LDV2CK1) ; 
  end 

  always @(posedge RST or posedge NX2)
  begin : cycle_counter
    if (RST)
    begin
      Q4 <= 1'b0 ; 
      Q5 <= 1'b0 ; 
    end
    else
    begin
      if (SMF & ~LDV2CK2)
      begin
        if (((Q4 ^ Q5)) & MULDIV)
        begin
          Q5 <= 1'b1 ; 
        end
        else
        begin
          Q5 <= 1'b0 ; 
        end 
        // GOCYC2 from the opcode decoder determines whether an instruction
        // requires a second machine cycle.
        // Only multiply and divide instructions enter cycles 3 and 4.
        if ((PCON[0] | Q4 | ~GOCYC2))
        begin
          Q4 <= 1'b0 ; 
        end
        else
        begin
          Q4 <= 1'b1 ; 
        end 
      end 
    end 
  end 
  //*********************************************************************
endmodule