m3s023bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// SFR Output Multiplexer sub-block of M8051
//Copyright Mentor graphics Corporation and Licensors 1998. All rights reserved
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:43 1998
//
// Input file : m3s023bo.vhd
// Design name : m3s023bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s023bo.vhd
//Created on    :       23th October 1995
//Purpose       :       SFR multiplexor sub-block of m8051
//Version       :       1.005
//Mod Date      :       2nd April 1998
//Mod History	:       1.005 _e suffix removed from entity names.
//                      1.004 Unused addresses no longer inject 'X's
//                      1.003 OPL and OPH changed to DPL and DPH 
//                      1.002-Calling file changed to m8051.vhd
//                      1.001(Original)
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//-------------------------------------------------
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s023bo (SFRDAT, FA, PORTA, PORTB, PORTC, PORTD, SP, DPL, DPH, PCON,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
TCON, TMOD, TLA, TLB, THA, THB, SCON, SBUF, IE, IP, PSWDAT, ACCDAT, BREG,
MSIZ);

  output[7:0] SFRDAT;
  reg[7:0] SFRDAT;
  input[6:0] FA;
  input[7:0] PORTA;
  input[7:0] PORTB;
  input[7:0] PORTC;
  input[7:0] PORTD;
  input[7:0] SP;
  input[7:0] DPL;
  input[7:0] DPH;
  input[7:0] PCON;
  input[7:0] TCON;
  input[7:0] TMOD;
  input[7:0] TLA;
  input[7:0] TLB;
  input[7:0] THA;
  input[7:0] THB;
  input[7:0] SCON;
  input[7:0] SBUF;
  input[7:0] IE;
  input[7:0] IP;
  input[7:0] PSWDAT;
  input[7:0] ACCDAT;
  input[7:0] BREG;
  input[7:0] MSIZ;

  //*********************************************************************
  //*********************************************************************
  //*********************************************************************
  // Sub-Multiplexer Outputs
  reg[7:0] SUB_SERIAL; 
  reg[7:0] SUB_TIMER; 
  reg[7:0] SUB_MISC; 

  always @(FA or PORTA or SP or DPL or DPH or PCON or TCON or TMOD or TLA or 
   TLB or THA or THB)
  begin : set_sub_muxes
    case (FA[2:0])
      3'b000 :
            begin
              SUB_TIMER <= TCON ; 
              SUB_MISC <= PORTA ; 
            end
      3'b001 :
            begin
              SUB_TIMER <= TMOD ; 
              SUB_MISC <= SP ; 
            end
      3'b010 :
            begin
              SUB_TIMER <= TLA ; 
              SUB_MISC <= DPL ; 
            end
      3'b011 :
            begin
              SUB_TIMER <= TLB ; 
              SUB_MISC <= DPH ; 
            end
      3'b100 :
            begin
              SUB_TIMER <= THA ; 
              SUB_MISC <= PORTA ; 
            end
      3'b101 :
            begin
              SUB_TIMER <= THB ; 
              SUB_MISC <= SP ; 
            end
      3'b110 :
            begin
              SUB_TIMER <= THA ; 
              SUB_MISC <= DPL ; 
            end
      3'b111 :
            begin
              SUB_TIMER <= THB ; 
              SUB_MISC <= PCON ; 
            end
      default :
            begin
              SUB_TIMER <= 8'bXXXXXXXX ; 
              SUB_MISC <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(FA or SCON or SBUF)
  begin : set_sub_serial
    case (FA[0])
      1'b0 :
            begin
              SUB_SERIAL <= SCON ; 
            end
      1'b1 :
            begin
              SUB_SERIAL <= SBUF ; 
            end
      default :
            begin
              SUB_SERIAL <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(FA or SUB_MISC or SUB_TIMER or PORTB or SUB_SERIAL or PORTC or 
   IE or PORTD or IP or PSWDAT or ACCDAT or BREG or MSIZ)
  begin : set_sfr
    case (FA[6:3])
      4'b0000 :
            begin
              SFRDAT <= SUB_MISC ; 
            end
      4'b0001 :
            begin
              SFRDAT <= SUB_TIMER ; 
            end
      4'b0010 :
            begin
              SFRDAT <= PORTB ; 
            end
      4'b0011 :
            begin
              SFRDAT <= SUB_SERIAL ; 
            end
      4'b0100 :
            begin
              SFRDAT <= PORTC ; 
            end
      4'b0101 :
            begin
              SFRDAT <= IE ; 
            end
      4'b0110 :
            begin
              SFRDAT <= PORTD ; 
            end
      4'b0111 :
            begin
              SFRDAT <= IP ; 
            end
      4'b1000 :
            begin
              SFRDAT <= PSWDAT ; 
            end
      4'b1001 :
            begin
              SFRDAT <= PSWDAT ; 
            end
      4'b1010 :
            begin
              SFRDAT <= PSWDAT ; 
            end
      4'b1011 :
            begin
              SFRDAT <= PSWDAT ; 
            end
      4'b1100 :
            begin
              SFRDAT <= ACCDAT ; 
            end
      4'b1101 :
            begin
              SFRDAT <= ACCDAT ; 
            end
      4'b1110 :
            begin
              SFRDAT <= BREG ; 
            end
      4'b1111 :
            begin
              SFRDAT <= MSIZ ; 
            end
      default :
            begin
              SFRDAT <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 
  //*********************************************************************
endmodule