m3s032bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// ALU Temporary Register Number 1 Control Decoder for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//v1.004
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:06:08 1998
//
// Input file : m3s032bo.vhd
// Design name : m3s032bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s032bo.vhd
//Created on    :       11th September 1995
//Purpose       :       Temporary Register Number 1 Control Decoder for M8051
//Version       :       1.004
//Mod Date      :       2nd April 1998
//Mod History	:	1.004 _e suffix removed from entity names.
//                      1.003 Name changes
//                      1.002 Name Changes and BRET decoder moved to
//                            module m3s004bo. Sensitivity list 
//                            revisions.
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s004bo.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s032bo (TMPADD, PCLONG, LO5TOF, NLOGDA, HIDEC, LODEC, LODEC_4TOF,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
ND16, MULDIV, NMPC, NLCA, NLJM, EITHER_RET, LOGDI);

  output[3:0] TMPADD;
  reg[3:0] TMPADD;
  output PCLONG;
  reg PCLONG;
  output LO5TOF;
  reg LO5TOF;
  output NLOGDA;
  reg NLOGDA;
  input[11:2] HIDEC;
  input[5:2] LODEC;
  input LODEC_4TOF;
  input ND16;
  input MULDIV;
  input NMPC;
  input NLCA;
  input NLJM;
  input EITHER_RET;
  input LOGDI;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg AA; 
  reg AB; 
  reg AC; 
  reg AD; 
  reg AE; 
  reg AF; 
  reg AH; 
  reg BA; 
  reg BB; 
  reg BC; 
  reg BD; 
  reg BE; 

  always @(HIDEC or LODEC or NLCA or NLJM or LODEC_4TOF or MULDIV or ND16)
  begin : misc1
    AA <= NLCA & NLJM ; 
    AB <= ~LODEC_4TOF | LODEC[5] ; 
    AC <= HIDEC[4] | HIDEC[5] | HIDEC[6] ; 
    AD <= HIDEC[2] | HIDEC[3] | HIDEC[9] ; 
    AE <= LODEC[5] & HIDEC[11] ; 
    AF <= LODEC[4] | ~LODEC_4TOF ; 
    AH <= ND16 & ~MULDIV ; 
  end 

  always @(AB or AC or AD or AE or AF or LODEC or HIDEC)
  begin : misc2
    BA <= LODEC[4] & AC ; 
    BB <= LODEC[4] & AD ; 
    BC <= LODEC[2] & AC ; 
    BD <= (AC | AD | AE) & ~AF ; 
    BE <= ~(AB | ~HIDEC[11]) ; 
  end 

  always @(AA or AH or BA or BB or BC or BD or BE or LOGDI or MULDIV or NMPC 
  or 
   EITHER_RET)
  begin : tmpout1
    TMPADD[0] <= LOGDI | ~AA | ~AH | BA | BB | BE ; 
    TMPADD[1] <= BC | BD | EITHER_RET | ~AH ; 
    TMPADD[2] <= ~MULDIV ; 
    TMPADD[3] <= ~NMPC ; 
  end 

  always @(AA or AF or BC)
  begin : miscout
    // Map local signal names to global names
    PCLONG <= ~AA ; 
    LO5TOF <= ~AF ; 
    NLOGDA <= ~BC ; 
  end 
  //*********************************************************************
endmodule