m3s033bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Accumulator, B Register and ALU Temporary Register 2 Control Decoder
//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.
//v1.004
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:06:11 1998
//
// Input file : m3s033bo.vhd
// Design name : m3s033bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s033bo.vhd
//Created on    :       11th September 1995
//Purpose       :       Acc, B Register and ALU Temporary Register 2 Control Decoder
//Version       :       1.004
//Mod Date      :       2nd April 1998
//Mod History	:       1.004 _e suffix removed from entity names.
//                      1.003 Name changes
//                      1.002 ECN 878: temp register 2 given extra load
//                            times.
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s004bo.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s033bo (ACCADD, NMOVPC, NINCDP, NSWAPN, NMOVBC, LOGDI, HIDEC, LODEC,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
OPC, LODEC_4TOF, NOP16, MULDIV, INDXR, INDOP, NDIV, NDJD, NDJR, NBEN, CJNE,
NMUL, NMCB);

  output[9:0] ACCADD;
  reg[9:0] ACCADD;
  output NMOVPC;
  reg NMOVPC;
  output NINCDP;
  reg NINCDP;
  output NSWAPN;
  reg NSWAPN;
  output NMOVBC;
  reg NMOVBC;
  output LOGDI;
  reg LOGDI;
  input[14:0] HIDEC;
  input[7:0] LODEC;
  input[7:3] OPC;
  input LODEC_4TOF;
  input NOP16;
  input MULDIV;
  input INDXR;
  input INDOP;
  input NDIV;
  input NDJD;
  input NDJR;
  input NBEN;
  input CJNE;
  input NMUL;
  input NMCB;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg AA; 
  reg AB; 
  reg AC; 
  reg AD; 
  reg AE; 
  reg AF; 
  reg AG; 
  reg AH; 
  reg AI; 
  reg AJ; 
  reg AK; 
  reg AL; 
  reg AM; 
  reg AN; 
  reg AP; 
  reg AQ; 
  reg BA; 
  reg BB; 
  reg BC; 
  reg BE; 
  reg BF; 
  reg CA; 
  reg CB; 

  always @(HIDEC or LODEC)
  begin : misc1
    AA <= HIDEC[7] & LODEC[4] ; 
    AB <= HIDEC[14] & LODEC[0] ; 
    AC <= HIDEC[8] & LODEC[3] ; 
    AD <= HIDEC[9] & LODEC[3] ; 
    AE <= HIDEC[12] | HIDEC[13] | HIDEC[14] ; 
    AF <= (HIDEC[12] | HIDEC[14]) & LODEC[5] ; 
    AG <= HIDEC[2] | HIDEC[3] | HIDEC[10] | HIDEC[11] | HIDEC[12] | HIDEC[
    13] ; 
    AH <= HIDEC[0] | HIDEC[1] | HIDEC[8] | HIDEC[10] ; 
    AI <= HIDEC[4] | HIDEC[5] | HIDEC[6] ; 
    AJ <= (LODEC[6] | LODEC[7]) & HIDEC[13] ; 
    AK <= HIDEC[10] & LODEC[3] ; 
    AL <= ~HIDEC[11] & LODEC[4] ; 
    AM <= HIDEC[14] & ~LODEC[1] ; 
    AN <= HIDEC[2] | HIDEC[3] | HIDEC[4] | HIDEC[5] ; 
    AP <= HIDEC[9] & LODEC[2] ; 
    AQ <= LODEC[4] | LODEC[5] ; 
  end 

  always @(HIDEC or OPC or AH or NDJD or NDJR or NBEN or NMCB or LODEC_4TOF or 
   LODEC)
  begin : misc2
    BA <= (HIDEC[12] | HIDEC[14]) & OPC[3] ; 
    BB <= NDJD & NDJR & NBEN & NMCB ; 
    BC <= ~AH | ~LODEC_4TOF | LODEC[4] ; 
  end 

  always @(AN or AQ or CJNE or HIDEC)
  begin : misc3
    BE <= AQ | ~CJNE ; 
    BF <= HIDEC[6] | HIDEC[9] | HIDEC[14] | AN ; 
  end 

  always @(AC or AD or LODEC_4TOF or AN or BB or BC or BF or AG or AI or LODEC)
  begin : misc4
    CA <= BB & BC & (~(AG & LODEC[0])) & (~(AI & LODEC[3])) ; 
    CB <= AC | AD | (LODEC_4TOF & BF) ; 
  end 

  always @(NDIV or NMUL or MULDIV or INDXR or INDOP or AA or AB or AC or 
   AD or AE or AF or BA or BE or CA)
  begin : accout1
    ACCADD[0] <= MULDIV | INDXR | AA | AB | AC | AD ; 
    ACCADD[1] <= MULDIV | AF | BA | (AE & INDOP) ; 
    ACCADD[2] <= ~NDIV ; 
    ACCADD[3] <= ~(NDIV & BE & CA & NMUL) ; 
    ACCADD[9] <= NDIV & ~(BE & CA & NMUL) ; 
  end 

  always @(AJ or NOP16 or AJ or AK or AL or AM or CB or LODEC or HIDEC or 
   OPC or LODEC_4TOF)
  begin : accout2
    ACCADD[4] <= AJ ; 
    ACCADD[5] <= ~NOP16 ; 
    ACCADD[6] <= AK ; 
    ACCADD[7] <= AL | AM | CB | (LODEC[3] & ~OPC[6] & ~OPC[7]) ; 
    ACCADD[8] <= AJ | (HIDEC[12] & LODEC_4TOF) ; 
  end 

  always @(AC or AI or AJ or AK or AP or LODEC)
  begin : miscout
    NMOVPC <= ~AC ; 
    LOGDI <= AI & LODEC[3] ; 
    NSWAPN <= ~AJ ; 
    NINCDP <= ~AK ; 
    NMOVBC <= ~AP ; 
  end 
  //*********************************************************************
endmodule