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📄 m3s016bo.v

📁 another 8051 core porocesssor vhdl source code
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//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      ////8-bit up counter for M8051//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.//v2.001//////////////////////////////////////////////////////////////////////////////////// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998// Thu Jul  9 22:05:25 1998//// Input file : m3s016bo.vhd// Design name : m3s016bo// Author : // Company : Mentor Graphics - Inventra//// Description : ////////////////////////////////////////////////////////////////////////////////////////*********************************************************************//%W% %G% SCCS Version Control//File	        :       m3s016bo.vhd//Created on    :       8th April 1997//Purpose       :       8-bit up counter for M8051//Version       :       2.001//Mod Date      :       2nd April 1998//Mod History	:       2.001 _e suffix removed from entity names.////*********************************************************************//Hierarchy record      ://Called by             :m3s015bo.vhd//                      ://Calls to              ://*********************************************************************//*********************************************************************//Entity Definition//*********************************************************************module m3s016bo (CO, CNT, MODE0, LD, CI, CLEAR, COUNT_EN, NX1, DIN);//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      //  output CO;  reg CO;  output[7:0] CNT;  reg[7:0] CNT;  input MODE0;  input LD;  input CI;  input CLEAR;  input COUNT_EN;  input NX1;  input[7:0] DIN;  //*********************************************************************  //signal definition  //*********************************************************************  reg[7:0] LCT;   reg C4;   always @(posedge NX1)  begin : set_count    if (CLEAR)    begin      LCT <= 8'b00000000 ;     end    else if (COUNT_EN)    begin      if (LD)      begin        LCT <= DIN ;       end      else      begin        LCT[0] <= LCT[0] ^ CI ;         LCT[1] <= LCT[1] ^ (CI & LCT[0]) ;         LCT[2] <= LCT[2] ^ (CI & LCT[0] & LCT[1]) ;         LCT[3] <= LCT[3] ^ (CI & LCT[0] & LCT[1] & LCT[2]) ;         LCT[4] <= LCT[4] ^ C4 ;         LCT[5] <= LCT[5] ^ (C4 & LCT[4]) ;         LCT[6] <= LCT[6] ^ (C4 & LCT[4] & LCT[5]) ;         LCT[7] <= LCT[7] ^ (C4 & LCT[4] & LCT[5] & LCT[6]) ;       end     end    end   always @(LCT or CI or MODE0)  begin : set_carry    // Generate counter carry out for five or eight bit modes with    // combinatorial dependence on the counter carry input.    // Map local variable to global name for export.    C4 <= CI & LCT[0] & LCT[1] & LCT[2] & LCT[3] ;     CO <= CI & LCT[0] & LCT[1] & LCT[2] & LCT[3] & LCT[4] & (MODE0 | (LCT[    5] & LCT[6] & LCT[7])) ;     CNT <= LCT ;   end   //*********************************************************************endmodule

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