m3s003bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// 8-Bit Arithmetic Logic Unit for m8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.
//v1.006
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:04:43 1998
//
// Input file : m3s003bo.vhd
// Design name : m3s003bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s003bo.vhd
//Created on    :       14th October 1995
//Purpose       :       2 x 4 bit ALU,with look ahead carry for m8051
//Version       :       1.006
//Mod Date      :       2nd April 1998
//Mod History	:       1.006 _e suffix removed from entity names.
//                      1.005 Look-ahead carry restored to design.
//                      1.004 Sensitivity list revisions, redundant
//                            decode removed.
//                      1.003-ECN 857-CARI in sensitivity list
//                      1.002-Calling file name changed to m8051.vhd
//                      1.001(Original)
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :m3s002bo.vhd
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s003bo (ALUDAT, CPRDDM, CO, ACO, OV, BBIT, ACLDAT, TMPDAT, ALUC,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
ACCDAT, BIT_POSN, NMULAB, NDIVAB, DAA, ACC0);

  output[7:0] ALUDAT;
  reg[7:0] ALUDAT;
  output[7:0] CPRDDM;
  reg[7:0] CPRDDM;
  output CO;
  reg CO;
  output ACO;
  reg ACO;
  output OV;
  reg OV;
  output BBIT;
  reg BBIT;
  input[9:0] ACLDAT;
  input[7:0] TMPDAT;
  input[17:0] ALUC;
  input[7:7] ACCDAT;
  input[2:0] BIT_POSN;
  input NMULAB;
  input NDIVAB;
  input DAA;
  input ACC0;

  //*********************************************************************
  //*********************************************************************
  //Component Definitions
  //*********************************************************************
  // ALU primitive components: bit slice and 4-bit carry look-ahead units
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg QCI; 
  reg CMUX; 
  reg CBEN; 
  reg CAM; 
  reg CARI; 
  reg LBBIT; 
  reg AA; 
  reg AB; 
  reg AC; 
  reg AD; 
  reg AE; 
  reg AF; 
  reg PROP_LO; 
  reg AH; 
  reg AR; 
  reg AS; 
  reg AT; 
  reg AU; 
  reg AV; 
  reg AW; 
  reg AAA; 
  reg AAB; 
  reg AAC; 
  reg AAD; 
  reg AAE; 
  reg AAF; 
  reg GEN_LO; 
  reg BB; 
  reg BC; 
  reg BD; 
  reg BE; 
  reg BF; 
  reg BG; 
  reg CA; 
  reg CB; 
  reg CC; 
  reg CD; 
  reg CE; 
  reg CF; 
  reg CG; 
  reg CH; 
  reg DA; 
  reg DB; 
  reg DC; 
  reg EJ; 
  reg EK; 
  reg LOCALA; 
  reg LOCALB; 
  reg LOCALC; 
  reg LOCALD; 
  reg LOCALE; 
  reg LOCALF; 
  wire[7:0] ALU_PROP; 
  wire[7:0] ALU_GEN; 
  wire[7:0] ALU_SUM; 
  reg[7:0] ALUP; 
  reg[7:0] LDATAA; 
  reg[1:0] muxvect1; 
  //*********************************************************************
  //Port Mapping
  //*********************************************************************
  //*********************************************************************
  m3s002bo U1 (.P(ALU_PROP[0]), .CO(ALU_GEN[0]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  0]), .B(TMPDAT[0])); 
  //*********************************************************************
  m3s002bo U2 (.P(ALU_PROP[1]), .CO(ALU_GEN[1]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  1]), .B(TMPDAT[1])); 
  //*********************************************************************
  m3s002bo U3 (.P(ALU_PROP[2]), .CO(ALU_GEN[2]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  2]), .B(TMPDAT[2])); 
  //*********************************************************************
  m3s002bo U4 (.P(ALU_PROP[3]), .CO(ALU_GEN[3]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  3]), .B(TMPDAT[3])); 
  //*********************************************************************
  m3s002bo U5 (.P(ALU_PROP[4]), .CO(ALU_GEN[4]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  4]), .B(TMPDAT[4])); 
  //*********************************************************************
  m3s002bo U6 (.P(ALU_PROP[5]), .CO(ALU_GEN[5]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  5]), .B(TMPDAT[5])); 
  //*********************************************************************
  m3s002bo U7 (.P(ALU_PROP[6]), .CO(ALU_GEN[6]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  6]), .B(TMPDAT[6])); 
  //*********************************************************************
  m3s002bo U8 (.P(ALU_PROP[7]), .CO(ALU_GEN[7]), .ALUC(ALUC[5:0]), .A(ACLDAT[
  7]), .B(TMPDAT[7])); 
  //*********************************************************************
  m3s041bo U9 (.S(ALU_SUM[3:0]), .P(ALU_PROP[3:0]), .G(ALU_GEN[2:0]), .C_IN(
  QCI), .C_EN(CBEN)); 
  //*********************************************************************
  m3s041bo U10 (.S(ALU_SUM[7:4]), .P(ALU_PROP[7:4]), .G(ALU_GEN[6:4]), .C_IN(
  DA), .C_EN(CBEN)); 

  always @(ALUC or ACC0 or DB or AV or NMULAB or NDIVAB)
  begin : general1
    CMUX <= (NMULAB | ACC0) & ((DB ^ AV) | NDIVAB) ; 
    CBEN <= ALUC[4] | ALUC[5] ; 
    CARI <= DB ^ AV ; 
  end 

  always @(CARI or CMUX or AAF or ALUC)
  begin : general2
    CAM <= CARI & CMUX ; 
    QCI <= ~(ALUC[5] ^ ~AAF) ; 
  end 

  always @(ALU_PROP or ALU_GEN or QCI or CBEN or LBBIT or ALUC or ACLDAT or 
   NDIVAB)
  begin : misc1
    AA <= ALU_GEN[0] & ALU_PROP[1] & ALU_PROP[2] & ALU_PROP[3] ; 
    AB <= ALU_GEN[1] & ALU_PROP[2] & ALU_PROP[3] ; 
    AC <= ALU_GEN[2] & ALU_PROP[3] ; 
    AD <= ALU_GEN[4] & ALU_PROP[5] & ALU_PROP[6] & ALU_PROP[7] ; 
    AE <= ALU_GEN[5] & ALU_PROP[6] & ALU_PROP[7] ; 
    AF <= ALU_GEN[6] & ALU_PROP[7] ; 
    PROP_LO <= ALU_PROP[0] & ALU_PROP[1] & ALU_PROP[2] & ALU_PROP[3] ; 
    AH <= ALU_PROP[4] & ALU_PROP[5] & ALU_PROP[6] & ALU_PROP[7] ; 
    AR <= (~ACLDAT[9]) & (~LBBIT) & ALUC[9] ; 
    AS <= (~ACLDAT[9]) & LBBIT & ALUC[10] ; 
    AT <= ACLDAT[9] & LBBIT & ALUC[11] ; 
    AU <= ACLDAT[9] & (~LBBIT) & ALUC[12] ; 
    AV <= ALUC[5] & NDIVAB ; 
    AW <= ALUC[7] & ALUC[15] ; 
  end 

  always @(AA or AB or AC or AD or AE or AF or AR or AS or AT or AU or AW or 
   AAA or AAB or AAD or AAE or ALU_GEN or ALUC or NMULAB or NDIVAB)
  begin : misc2
    GEN_LO <= AA | AB | AC | ALU_GEN[3] ; 
    BB <= AD | AE | AF | ALU_GEN[7] ; 
    BC <= AR | AS | AT | AU ; 
    BD <= AW | ~ALUC[14] ; 
    BE <= AAA | AAB | ALU_GEN[6] ; 
    BF <= AAD & ~NMULAB ; 
    BG <= AAE | NDIVAB ; 
  end 

  always @(PROP_LO or AH or GEN_LO or BB or BE or BF or BG or AAC or QCI)
  begin : misc3
    CA <= (QCI | GEN_LO) & (GEN_LO | PROP_LO) ; 
    CB <= QCI | GEN_LO | BB ; 
    CC <= PROP_LO | GEN_LO | BB ; 
    CD <= BB | AH ; 
    CE <= QCI | GEN_LO | BE ; 
    CF <= PROP_LO | GEN_LO | BE ; 
    CG <= AAC | BE ; 
    CH <= BF | ~BG ; 
  end 

  always @(CA or CB or CC or CD or CE or CF or CG or CBEN)
  begin : misc4
    DA <= CA & CBEN ; 
    DB <= CB & CC & CD ; 
    DC <= CE & CF & CG ; 
  end 

  always @(DC or CARI or LOCALF or DAA or ALUC)
  begin : misc5
    EJ <= LOCALF | (DAA & CARI) ; 
    EK <= (DC ^ ALUC[5]) ^ CARI ; 
  end 

  always @(ALU_GEN or ALU_PROP or ALUP or TMPDAT or ACLDAT or ALUC or CBEN)
  begin : misc6
    AAA <= ALU_GEN[4] & ALU_PROP[5] & ALU_PROP[6] ; 
    AAB <= ALU_GEN[5] & ALU_PROP[6] ; 
    AAC <= ALU_PROP[4] & ALU_PROP[5] & ALU_PROP[6] ; 
    AAD <= ALUP[0] | ALUP[1] | ALUP[2] | ALUP[3] | ALUP[4] | ALUP[5] | ALUP[
    6] | ALUP[7] ; 
    AAE <= TMPDAT[0] | TMPDAT[1] | TMPDAT[2] | TMPDAT[3] | TMPDAT[4] | TMPDAT[
    5] | TMPDAT[6] | TMPDAT[7] ; 
    AAF <= ACLDAT[9] & ALUC[13] & CBEN ; 
  end 

  always @(ALU_SUM or ACLDAT or CMUX)
  begin : set_dataa