m8051.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//M8051 Soft Core Top Level
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//Core Version 6.7 for revision history see m8051.readme
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:06:32 1998
//
// Input file : m8051.vhd
// Design name : m8051
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m8051.vhd
//Created on    :       9th January 1996
//Purpose       :       M8051 Megamacro 
//Version       :       1.013
//Mod Date      :       2nd April 1998
//Mod History	:       1.013 _e suffix removed from entity names.
//                      1.012 Redundant signals removed, comments added.
//                      1.011 SFR Expansion Capability
//                      1.010 Name change for Verilog translation.
//                      1.009 Name changes and exports.
//                            Program counter revisions.
//                            Sensitivity list revisions.
//                            Use accumulator not ALUDAT for MOVX writes
//                      1.008 ECN 878: PCADD bus width increased, C_TRUE
//                            inserted into m3s010bo and m3s008bo.
//                            Read Modify Write affects timer counters. 
//                      1.007 LDV1 renamed LOV1
//			1.006 Idle Mode Power Saving Scheme
//			1.005-ACCO changed to ACC0,OPH,OPL changed
//                            to DPH and DPL 
//                            ECN 863 ALEN brought forward to end of reset   
//                      1.004-ECN838 adjustment to OPC timing
//                           -and dummy address matching 
//                      1.003-Change to download mode
//                      1.002-File name changed from m3s000bo.vhd
//                      1.001(Original)
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051_tb.vhd
//Calls to              :m3s001bo.vhd
//                      :m3s003bo.vhd
//                      :m3s004bo.vhd
//                      :m3s005bo.vhd
//                      :m3s006bo.vhd
//                      :m3s007bo.vhd
//                      :m3s008bo.vhd
//                      :m3s010bo.vhd
//                      :m3s015bo.vhd
//                      :m3s018bo.vhd
//                      :m3s019bo.vhd
//                      :m3s020bo.vhd
//                      :m3s023bo.vhd
//                      :m3s025bo.vhd
//                      :m3s028bo.vhd
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m8051 (NMOE, NMWE, DLM, ALE, NPSEN, NALEN, NFWE, NFOE, NSFRWE, NSFROE,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
IDLE, XOFF, OA, OB, OC, OD, AE, BE, CE, DE, FA, FO, M, NX1, NX2, RST, NEA,
NESFR, ALEI, PSEI, AI, BI, CI, DI, FI, MD);

  output NMOE;
  reg NMOE;
  output NMWE;
  reg NMWE;
  output DLM;
  reg DLM;
  output ALE;
  wire ALE;
  output NPSEN;
  wire NPSEN;
  output NALEN;
  reg NALEN;
  output NFWE;
  wire NFWE;
  output NFOE;
  wire NFOE;
  output NSFRWE;
  wire NSFRWE;
  output NSFROE;
  wire NSFROE;
  output IDLE;
  reg IDLE;
  output XOFF;
  reg XOFF;
  output[7:0] OA;
  reg[7:0] OA;
  output[7:0] OB;
  wire[7:0] OB;
  output[7:0] OC;
  wire[7:0] OC;
  output[7:0] OD;
  wire[7:0] OD;
  output[7:0] AE;
  wire[7:0] AE;
  output[7:0] BE;
  wire[7:0] BE;
  output[7:0] CE;
  wire[7:0] CE;
  output[7:0] DE;
  wire[7:0] DE;
  output[7:0] FA;
  reg[7:0] FA;
  output[7:0] FO;
  reg[7:0] FO;
  output[15:0] M;
  reg[15:0] M;
  input NX1;
  input NX2;
  input RST;
  input NEA;
  input NESFR;
  input ALEI;
  input PSEI;
  input[7:0] AI;
  input[7:0] BI;
  input[7:0] CI;
  input[7:0] DI;
  input[7:0] FI;
  input[7:0] MD;

  //*********************************************************************
  //*********************************************************************
  //Component Definitions
  //*********************************************************************
  //Clock Generator
  //*********************************************************************
  //ALU
  //*********************************************************************
  //Opcode decode
  //*********************************************************************
  //Accumulator and ALU Input Temporary Register Number 2
  //*********************************************************************
  // ALU Input Temporary Register Number 1
  //*********************************************************************
  //Conditional Branch Test
  //*********************************************************************
  //Register control
  //*********************************************************************
  //Program counter control
  //*********************************************************************
  //Timer counter
  //*********************************************************************
  //I/O port control
  //*********************************************************************
  //Interrupt control
  //even bits not used
  //*********************************************************************
  //miscellaneous special function registers
  //*********************************************************************
  //special function register output multiplexer
  //*********************************************************************
  //Opcode Register
  //*********************************************************************
  //UART
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  wire DIV2CK1; 
  wire DIV2CK2; 
  reg CLEAR; 
  wire NMULAB; 
  wire NDIVAB; 
  wire LCYC; 
  wire GOCYC2; 
  wire MULDIV; 
  wire S_EN; 
  wire T_EN; 
  wire STATE12; 
  wire LOGDI; 
  wire C_TRUE; 
  wire DAAL; 
  wire DAAH; 
  wire DAA; 
  wire EXPMEM; 
  wire INTA; 
  wire OPLOAD; 
  wire RETI; 
  wire RMW; 
  wire PAR; 
  wire ACC0; 
  wire ACO; 
  wire BBIT; 
  wire CO; 
  wire IMMB3; 
  wire IMMB4; 
  wire OV; 
  wire RESINT; 
  wire WEP; 
  reg DLMR; 
  reg DLMSTB; 
  reg DLMSTBI; 
  wire RITI; 
  wire RXDO; 
  wire TXDO; 
  wire LOV1; 
  wire MOEI; 
  reg IMMDATEN; 
  wire JMPADPTR; 
  reg LDLM; 
  wire EXT_PROG_EN; 
  wire EXT_ROM; 
  wire JBC; 
  wire CJNE; 
  wire EITHER_RET; 
  wire ADDR_11BIT; 
  wire[2:0] CODAT;