m3s010bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Program Counter Control for M8051
//(c) Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.010
//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:08 1998
//
// Input file : m3s010bo.vhd
// Design name : m3s010bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s010bo.vhd
//Created on    :       28th Dec 1995
//Purpose       :       PC control for M8051
//Version       :       1.010
//Mod Date      :       2nd April 1998
//Mod History	:       1.010 _e suffix removed from entity names.
//                      1.009 STATDs 7-12 abandoned, redundant nets
//                            excised.
//                      1.008 Name change for Verilog translation
//                      1.007 PC MUX controls re-written for synthesis.
//                            EXT_PROG_EN and MOVC MUX moved in from
//                            m3s018bo. Program address busses revised.
//                            Sensitivity list revisions.
//                      1.006 ECN 878: Fast decision path for jump
//                            relatives
//			1.006 Unconditional look-ahead vector generation
//			1.005 OPH and OPL changed to DPH and DPL
//                      1.004-ECN 838 adjustment of OPC timing and
//                            dummy address cycle matching
//                      1.003- Change for download mode
//                      1.002-Calling file name changed to m8051.vhd
//                            LADD output removed
//                      1.001(Original)
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :m3s013bo.vhd
//                      :m3s011bo.vhd
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s010bo (EXT_PROG_EN, EXT_ROM, DPL, DPH, STACK_DATA, PROGRAM_COUNT,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
PROGRAM_ADDR, NEA, LCYC, DLM, DLMSTB, INTA, IDLE, C_TRUE, ADDR_11BIT, JMPADPTR,
CLEAR, DIV2CK, NX1, VECTOR_ADDR, RDAT, ALUDAT, IMMDAT, RAMDI, MSIZ, CYC, 
OPC, PCADD, STATD, SFRW);

  output EXT_PROG_EN;
  reg EXT_PROG_EN;
  output EXT_ROM;
  reg EXT_ROM;
  output[7:0] DPL;
  reg[7:0] DPL;
  output[7:0] DPH;
  reg[7:0] DPH;
  output[15:0] STACK_DATA;
  reg[15:0] STACK_DATA;
  output[15:0] PROGRAM_COUNT;
  reg[15:0] PROGRAM_COUNT;
  output[15:0] PROGRAM_ADDR;
  reg[15:0] PROGRAM_ADDR;
  input NEA;
  input LCYC;
  input DLM;
  input DLMSTB;
  input INTA;
  input IDLE;
  input C_TRUE;
  input ADDR_11BIT;
  input JMPADPTR;
  input CLEAR;
  input DIV2CK;
  input NX1;
  input[4:1] VECTOR_ADDR;
  input[7:0] RDAT;
  input[7:0] ALUDAT;
  input[7:0] IMMDAT;
  input[7:0] RAMDI;
  input[7:0] MSIZ;
  input[2:1] CYC;
  input[7:5] OPC;
  input[12:1] PCADD;
  input[6:1] STATD;
  input[15:14] SFRW;

  //*********************************************************************
  //*********************************************************************
  // Component Definitions
  //*********************************************************************
  //PC Inc/jump
  //*********************************************************************
  //pc mux
  //*********************************************************************
  //*********************************************************************
  //signal definitions
  //*********************************************************************
  reg AG; 
  reg BA; 
  reg JMP_REL; 
  reg L_EXT_ROM; 
  reg PC_INCR; 
  reg NFBH; 
  reg NFBL; 
  reg SEL_11BIT_ADDR; 
  reg PROGRAM_COUNT_EN; 
  reg STACK_DATA_EN; 
  reg DPL_EN; 
  reg DPH_EN; 
  reg[7:0] DPTR_DATA; 
  reg[7:0] LOCALA; 
  reg[7:0] ADDR_16BIT_LOW; 
  wire[15:0] NEXT_PROGRAM_COUNT; 
  reg[15:0] NEXT_PROGRAM_ADDR; 
  wire[15:0] NEXT_REL_PC; 
  reg[15:0] L_PROGRAM_COUNT; 
  //*********************************************************************
  //*********************************************************************
  //port mapping
  //*********************************************************************
  //*********************************************************************
  m3s011bo U1 (.NEXT_REL_PC(NEXT_REL_PC), .PROGRAM_COUNT(L_PROGRAM_COUNT),
  .IMMDAT(IMMDAT), .PC_INCR(PC_INCR), .JMP_REL(JMP_REL)); 
  //*********************************************************************
  m3s013bo U2 (.NEXT_PROGRAM_COUNT(NEXT_PROGRAM_COUNT), .VECTOR_ADDR(VECTOR_ADDR),
  .IMMDAT(IMMDAT), .ALUDAT(ALUDAT), .RDAT(RDAT), .OPC(OPC), .NEXT_REL_PC(NEXT_REL_PC),
  .PCADD(PCADD[2:1]), .NFBL(NFBL), .NFBH(NFBH), .SEL_11BIT_ADDR(SEL_11BIT_ADDR),
  .INTA(INTA)); 

  always @(STATD or CYC or PCADD or SFRW or AG)
  begin : gen1
    STACK_DATA_EN <= (CYC[1] & STATD[5] & PCADD[10]) | (CYC[1] & STATD[2]) ; 
    DPL_EN <= (SFRW[14] & PCADD[8]) | (AG & ~PCADD[8]) ; 
    DPH_EN <= (SFRW[15] & PCADD[8]) | (STATD[6] & CYC[1] & ~PCADD[8]) ; 
  end 

  always @(STATD or CYC or PCADD)
  begin : misc1
    AG <= (CYC[1] & PCADD[7] & STATD[3]) | (CYC[2] & STATD[6] & ~PCADD[7]) ; 
  end 

  always @(posedge NX1)
  begin : pc_load_controller
    // Determine whether program counter loads from brancher/incrementer
    // (the default condition) or from another source.  Loading from
    // another source normally takes place for both bytes at c2s4p1,
    // with the exception of the JMP @A+DPTR instruction. 
    // These signals are registered to break a combinatorial path from
    // the opcode to the program counter, for the benefit of synthesis
    // tools.
    // Jump and call instructions using 11-bit addresses load upper three
    // address bits from the opcode register.
    if (DLM)
    begin
      NFBL <= 1'b0 ; 
      NFBH <= 1'b0 ; 
      SEL_11BIT_ADDR <= 1'b0 ; 
    end
    else if (STATD[2] & ~DIV2CK)
    begin
      NFBL <= (CYC[2] ^ JMPADPTR) & ~PCADD[3] ; 
      NFBH <= CYC[2] & ~JMPADPTR & PCADD[4] ; 
      SEL_11BIT_ADDR <= ~DLM & CYC[2] & ADDR_11BIT ; 
    end
    else if (STATD[5] & ~DIV2CK)
    begin
      NFBL <= 1'b0 ; 
      NFBH <= CYC[1] & JMPADPTR & PCADD[4] ; 
      SEL_11BIT_ADDR <= 1'b0 ; 
    end  
  end 

  always @(posedge NX1)
  begin : misc2
    // Look ahead logic for program counter incrementer.
    // The program counter will always increment after an opcode load.
    if (STATD[1] & ~DIV2CK)
    begin
      BA <= (PCADD[9] & CYC[1]) | (PCADD[11] & CYC[2]) ; 
    end
    else if (STATD[4] & ~DIV2CK)
    begin
      BA <= LCYC | (PCADD[10] & CYC[1]) ; 
    end  
  end 

  always @(DLM or INTA or BA)
  begin : determine_carry
    // Determine whether a program counter increment is required.
    PC_INCR <= DLM | (BA & ~INTA) ; 
  end 

  always @(posedge NX1)
  begin : set_rel
    // Determine whether a relative jump calculation is required.
    if (DLM | (STATD[4] & ~DIV2CK))
    begin
      JMP_REL <= 1'b0 ; 
    end
    else if (STATD[1] & ~DIV2CK)
    begin
      JMP_REL <= CYC[2] & (PCADD[5] | PCADD[12]) ; 
    end  
  end 

  always @(DLM or STATD or IDLE or PCADD or CYC or C_TRUE)
  begin : pc_load_enable
    // Program counter is updated at the end of every S1P1 and S4P1
    // with the exception that no load takes place during conditional branch
    // instructions at C2S5P1 if the branch condition (C_TRUE) is not met.
    PROGRAM_COUNT_EN <= ~DLM & ((STATD[1] & ~IDLE) | (STATD[4] & (CYC[1] |
    ~(PCADD[5]) | C_TRUE))) ; 
  end 

  always @(posedge NX1)
  begin : update_program_counter
    // The Program Counter is updated at the end of S1P1 and S4P1.
    if (CLEAR & ~DLM)
    begin
      L_PROGRAM_COUNT <= 16'b0000000000000000 ; 
    end
    else if ((PROGRAM_COUNT_EN & DIV2CK) | DLMSTB)
    begin
      L_PROGRAM_COUNT[15:0] <= NEXT_PROGRAM_COUNT[15:0] ; 
    end  
  end 

  always @(posedge NX1)
  begin : save_addr16_low
    // save low part of 16-bit address from ALU in cycle 1 for use in
    // cycle 2.
    if (CYC[1] & STATD[3] & ~DIV2CK)
    begin
      ADDR_16BIT_LOW <= ALUDAT ; 
    end  
  end 

  always @(L_PROGRAM_COUNT or ALUDAT or ADDR_16BIT_LOW or PCADD or CYC or 
  STATD)
  begin : select_movc_addr
    if (PCADD[6] & CYC[2] & STATD[1])
    begin
      NEXT_PROGRAM_ADDR[15:8] <= ALUDAT ; 
      NEXT_PROGRAM_ADDR[7:0] <= ADDR_16BIT_LOW ; 
    end
    else
    begin
      NEXT_PROGRAM_ADDR <= L_PROGRAM_COUNT ; 
    end 
  end 

  always @(MSIZ or NEXT_PROGRAM_ADDR)
  begin : select_program_source
    if (NEXT_PROGRAM_ADDR[15:8] > MSIZ)
    begin
      L_EXT_ROM <= 1'b1 ; 
    end
    else
    begin
      L_EXT_ROM <= 1'b0 ; 
    end 
  end 

  always @(posedge NX1)
  begin : update_program_address
    // program address updates at the end of every S1P2 and S4P2 and
    // generally follows the program counter except during MOVC and 
    // JMP@A+DPTR instructions.  Update external program memory enable.
    if (CLEAR & ~STATD[4] & ~STATD[5] & ~DLM)
    begin
      PROGRAM_ADDR <= 16'b0000000000000000 ; 
      EXT_PROG_EN <= 1'b0 ; 
    end
    else if ((((STATD[1] & ~(JMPADPTR & CYC[2])) | (STATD[4] & ~(JMPADPTR &
    CYC[1]))) & ~DIV2CK) | DLM)
    begin
      PROGRAM_ADDR <= NEXT_PROGRAM_ADDR ; 
      EXT_PROG_EN <= (L_EXT_ROM | ~NEA) & ~DLM ; 
    end  
  end 

  always @(posedge NX1)
  begin : save_stack_data
    if (STACK_DATA_EN & DIV2CK)
    begin
      STACK_DATA[15:0] <= NEXT_REL_PC[15:0] ; 
    end  
  end 

  always @(posedge NX1)
  begin : set_data_pointer
    if (CLEAR)
    begin
      DPL <= 8'b00000000 ; 
      DPH <= 8'b00000000 ; 
    end
    else
    begin
      if (DPL_EN & ~DIV2CK)
      begin
        DPL <= DPTR_DATA ; 
      end 
      // load data pointer special function registers
      if (DPH_EN & ~DIV2CK)
      begin
        DPH <= DPTR_DATA ; 
      end 
    end  
  end 

  always @(PCADD or IMMDAT or ALUDAT)
  begin : muxlocala
    if (!(PCADD[7]))
    begin
      LOCALA[7:0] <= IMMDAT[7:0] ; 
    end
    else
    begin
      LOCALA[7:0] <= ALUDAT[7:0] ; 
    end 
  end 

  always @(PCADD or LOCALA or RAMDI)
  begin : muxop
    if (!(PCADD[8]))
    begin
      DPTR_DATA[7:0] <= LOCALA[7:0] ; 
    end
    else
    begin
      DPTR_DATA[7:0] <= RAMDI[7:0] ; 
    end 
  end 

  always @(L_PROGRAM_COUNT or L_EXT_ROM)
  begin : localout
    PROGRAM_COUNT <= L_PROGRAM_COUNT ; 
    EXT_ROM <= L_EXT_ROM ; 
  end 
  //********************************************************************* 
  //********************************************************************* 
endmodule