m3s030bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//TX shift register for UART of M8051
//Copyright Mentor Graphics Corporation and Licensors 1998.  All rights reserved
//v1.002
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:06:04 1998
//
// Input file : m3s030bo.vhd
// Design name : m3s030bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s030bo.vhd
//Created on    :       14th Dec 1995
//Purpose       :       TX shift register for UART of M8051
//Version       :       1.002
//Mod Date      :       2nd April 1998
//Mod History	:       1.002 _e suffix removed from entity names.
//
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s028bo.vhd
//                      :
//                      :
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s030bo (SOUT, QLOW, NEWDATA, CLEAR, TSHIFT_EN, TSHIFT_IN, NX1, RAMDI);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //

  output SOUT;
  reg SOUT;
  output QLOW;
  reg QLOW;
  input NEWDATA;
  input CLEAR;
  input TSHIFT_EN;
  input TSHIFT_IN;
  input NX1;
  input[7:0] RAMDI;

  //*********************************************************************
  //*********************************************************************
  //signal definition
  //*********************************************************************
  reg[7:0] DAT; 

  always @(posedge NX1)
  begin : mrshifter
    if (CLEAR)
    begin
      DAT <= 8'b00000000 ; 
    end
    else if (TSHIFT_EN)
    begin
      if (NEWDATA)
      begin
        DAT <= RAMDI ; 
      end
      else
      begin
        DAT[0] <= DAT[1] ; 
        DAT[1] <= DAT[2] ; 
        DAT[2] <= DAT[3] ; 
        DAT[3] <= DAT[4] ; 
        DAT[4] <= DAT[5] ; 
        DAT[5] <= DAT[6] ; 
        DAT[6] <= DAT[7] ; 
        DAT[7] <= TSHIFT_IN ; 
      end 
    end  
  end 

  always @(DAT)
  begin : set_outs
    SOUT <= DAT[0] ; 
    QLOW <= ~(DAT[7] | DAT[6] | DAT[5] | DAT[4] | DAT[3] | DAT[2]) ; 
  end 
  //*********************************************************************
endmodule