m3s022bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//matrix decode of m8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//v1.002
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:41 1998
//
// Input file : m3s022bo.vhd
// Design name : m3s022bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s022bo.vhd
//Created on    :       11th September 1995
//Purpose       :       matrix decode of m8051
//Version       :       1.002
//Mod Date      :       2nd April 1998
//Mod History	:       1.002 _e suffix removed from entity names.
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s004bo.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s022bo (LODEC, HIDEC, OPC);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //

  output[7:0] LODEC;
  reg[7:0] LODEC;
  output[15:0] HIDEC;
  reg[15:0] HIDEC;
  input[7:0] OPC;

  always @(OPC)
  begin : matr
    LODEC[0] <= ~(OPC[0] | OPC[1] | OPC[2] | OPC[3]) ; 
    LODEC[1] <= ~((~OPC[0]) | OPC[1] | OPC[2] | OPC[3]) ; 
    LODEC[2] <= ~(OPC[0] | (~OPC[1]) | OPC[2] | OPC[3]) ; 
    LODEC[3] <= ~((~OPC[0]) | (~OPC[1]) | OPC[2] | OPC[3]) ; 
    LODEC[4] <= ~(OPC[0] | OPC[1] | (~OPC[2]) | OPC[3]) ; 
    LODEC[5] <= ~((~OPC[0]) | OPC[1] | (~OPC[2]) | OPC[3]) ; 
    LODEC[6] <= ~(OPC[0] | (~OPC[1]) | (~OPC[2]) | OPC[3]) ; 
    LODEC[7] <= ~((~OPC[0]) | (~OPC[1]) | (~OPC[2]) | OPC[3]) ; 
    HIDEC[0] <= ~(OPC[4] | OPC[5] | OPC[6] | OPC[7]) ; 
    HIDEC[1] <= ~((~OPC[4]) | OPC[5] | OPC[6] | OPC[7]) ; 
    HIDEC[2] <= ~(OPC[4] | (~OPC[5]) | OPC[6] | OPC[7]) ; 
    HIDEC[3] <= ~((~OPC[4]) | (~OPC[5]) | OPC[6] | OPC[7]) ; 
    HIDEC[4] <= ~(OPC[4] | OPC[5] | (~OPC[6]) | OPC[7]) ; 
    HIDEC[5] <= ~((~OPC[4]) | OPC[5] | (~OPC[6]) | OPC[7]) ; 
    HIDEC[6] <= ~(OPC[4] | (~OPC[5]) | (~OPC[6]) | OPC[7]) ; 
    HIDEC[7] <= ~((~OPC[4]) | (~OPC[5]) | (~OPC[6]) | OPC[7]) ; 
    HIDEC[8] <= ~(OPC[4] | OPC[5] | OPC[6] | (~OPC[7])) ; 
    HIDEC[9] <= ~((~OPC[4]) | OPC[5] | OPC[6] | (~OPC[7])) ; 
    HIDEC[10] <= ~(OPC[4] | (~OPC[5]) | OPC[6] | (~OPC[7])) ; 
    HIDEC[11] <= ~((~OPC[4]) | (~OPC[5]) | OPC[6] | (~OPC[7])) ; 
    HIDEC[12] <= ~(OPC[4] | OPC[5] | (~OPC[6]) | (~OPC[7])) ; 
    HIDEC[13] <= ~((~OPC[4]) | OPC[5] | (~OPC[6]) | (~OPC[7])) ; 
    HIDEC[14] <= ~(OPC[4] | (~OPC[5]) | (~OPC[6]) | (~OPC[7])) ; 
    HIDEC[15] <= ~((~OPC[4]) | (~OPC[5]) | (~OPC[6]) | ~OPC[7]) ; 
  end 
  //*********************************************************************
endmodule