m3s005bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Accumulator and ALU Temporary Register Number 2 for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.007
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:04:53 1998
//
// Input file : m3s005bo.vhd
// Design name : m3s005bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s005bo.vhd
//Created on    :       3rd September 1995
//Purpose       :       Accumulator and temp2 latch sub block for m8051
//Version       :       1.007
//Mod Date      :       2nd April 1998
//Mod History	:       1.007 _e suffix removed from entity names.
//                      1.006 Redundant declarations removed.
//                      1.005 parity tree corrected.
//                      1.004 ECN 878: Read-modify-write instructions 
//                            use c2s2p2 to load ALU temp register 2.
//                            All temp & Accumulator loads now take
//                            place at the end of phase 2.
//                      1.003- ACCO name changed to ACC0
//                      1.002-Calling file changed to m8051.vhd
//                      1.001(Original)
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s005bo (ACCDAT, BREG, ACLDAT, PAR, ACC0, DAAL, DAAH, CYC, PSWDAT,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
STATD, ACCADD, ALUDAT, CPRDDM, RDAT, IMMDAT, RAMDI, SFRW, DAA, LCYC, DIV2CK,
CO, RST, NX1);

  output[7:0] ACCDAT;
  reg[7:0] ACCDAT;
  output[7:0] BREG;
  reg[7:0] BREG;
  output[9:0] ACLDAT;
  reg[9:0] ACLDAT;
  output PAR;
  reg PAR;
  output ACC0;
  reg ACC0;
  output DAAL;
  reg DAAL;
  output DAAH;
  reg DAAH;
  input[1:1] CYC;
  input[7:6] PSWDAT;
  input[6:2] STATD;
  input[9:0] ACCADD;
  input[7:0] ALUDAT;
  input[7:0] CPRDDM;
  input[7:0] RDAT;
  input[7:0] IMMDAT;
  input[7:0] RAMDI;
  input[21:20] SFRW;
  input DAA;
  input LCYC;
  input DIV2CK;
  input CO;
  input RST;
  input NX1;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg MULDIV; 
  reg AD; 
  reg AE; 
  reg AF; 
  reg AG; 
  reg AH; 
  reg AI; 
  reg AJ; 
  reg BD; 
  reg BE; 
  reg BF; 
  reg ACC_EN; // register load controls
  reg TEMP2_EN; // register load controls
  reg B_REG_EN; // register load controls
  reg BIT0MOD; 
  reg ADD2MOD; 
  reg ADD3MOD; 
  reg[1:0] MUXVECT1; 
  reg[1:0] MUXVECT2; 
  reg[1:0] MUXVECT3; 
  reg[7:0] LDATAA; 
  reg[7:0] LDATAB; 
  reg[7:0] LDATAC; 
  reg[7:0] LDATAD; 
  reg[7:0] REGMOD; 
  reg[7:0] ALUMOD; 
  reg[7:0] L_ACCDAT; 

  always @(ACCADD or ALUMOD or IMMDAT or REGMOD or LDATAB)
  begin : set_ldataa
    case (ACCADD[1:0])
      2'b00 :
            begin
              LDATAA <= ALUMOD ; 
            end
      2'b01 :
            begin
              LDATAA <= IMMDAT ; 
            end
      2'b10 :
            begin
              LDATAA <= REGMOD ; 
            end
      2'b11 :
            begin
              LDATAA <= LDATAB ; 
            end
      default :
            begin
              LDATAA <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(ACCADD or L_ACCDAT or CO)
  begin : set_ldatab
    case (ACCADD[2])
      1'b0 :
            begin
              LDATAB[6:0] <= L_ACCDAT[7:1] ; 
              LDATAB[7] <= CO ; 
            end
      1'b1 :
            begin
              LDATAB[7:1] <= L_ACCDAT[6:0] ; 
              LDATAB[0] <= CO ; 
            end
      default :
            begin
              LDATAB <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(ADD3MOD or ADD2MOD)
  begin : setmuxvect1
    MUXVECT1 <= {ADD3MOD, ADD2MOD} ; 
  end 

  always @(MUXVECT1 or L_ACCDAT or RDAT or BIT0MOD or ALUDAT)
  begin : set_ldatac
    case (MUXVECT1)
      2'b00 :
            begin
              LDATAC <= L_ACCDAT ; 
            end
      2'b01 :
            begin
              LDATAC[0] <= BIT0MOD ; 
              LDATAC[7:1] <= 7'b0000000 ; 
            end
      2'b10 :
            begin
              LDATAC <= RDAT ; 
            end
      2'b11 :
            begin
              LDATAC <= ALUDAT ; 
            end
      default :
            begin
              LDATAC <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(ACCADD or SFRW)
  begin : setmuxvect2
    MUXVECT2 <= {SFRW[20], ACCADD[2]} ; 
  end 

  always @(ALUDAT or CPRDDM or RAMDI or MUXVECT2)
  begin : set_ldatad
    case (MUXVECT2)
      2'b00 :
            begin
              LDATAD <= ALUDAT ; 
            end
      2'b01 :
            begin
              LDATAD <= CPRDDM ; 
            end
      2'b10 :
            begin
              LDATAD <= RAMDI ; 
            end
      2'b11 :
            begin
              LDATAD <= RAMDI ; 
            end
      default :
            begin
              LDATAD <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(BD or BE)
  begin : setmuxvect3
    MUXVECT3 <= {BD, BE} ; 
  end 

  always @(MUXVECT3 or L_ACCDAT or CO)
  begin : gencon1
    case (MUXVECT3)
      2'b00 :
            begin
              BIT0MOD <= 1'b0 ; 
            end
      2'b01 :
            begin
              BIT0MOD <= CO ; 
            end
      2'b10 :
            begin
              BIT0MOD <= L_ACCDAT[7] ; 
            end
      2'b11 :
            begin
              BIT0MOD <= 1'b1 ; 
            end
      default :
            begin
              BIT0MOD <= 1'bx ; 
            end
    endcase 
  end 

  always @(MULDIV or AD or AF or BF or ACCADD)
  begin : gencon2
    ADD3MOD <= ACCADD[3] & ~BF ; 
    ADD2MOD <= MULDIV | AD | AF ; 
  end 

  always @(ACCADD or RDAT or L_ACCDAT)
  begin : gencon3
    case (ACCADD[4])
      1'b0 :
            begin
              REGMOD[7:4] <= RDAT[7:4] ; 
            end
      1'b1 :
            begin
              REGMOD[7:4] <= L_ACCDAT[7:4] ; 
            end
      default :
            begin
              REGMOD[7:4] <= 4'bXXXX ; 
            end
    endcase 
  end 

  always @(SFRW or ALUDAT or RAMDI)
  begin : gencon4
    case (SFRW[21])
      1'b0 :
            begin
              ALUMOD <= ALUDAT ; 
            end
      1'b1 :
            begin
              ALUMOD <= RAMDI ; 
            end
      default :
            begin
              ALUMOD <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(STATD or ACCADD or L_ACCDAT or PSWDAT or CYC)
  begin : misc1
    MULDIV <= ACCADD[0] & ACCADD[1] ; 
    AD <= STATD[2] & ACCADD[6] ; 
    AE <= CYC[1] & STATD[2] & ACCADD[2] ; 
    AF <= STATD[5] & ACCADD[5] ; 
    AG <= STATD[2] & PSWDAT[6] ; 
    AH <= STATD[5] & PSWDAT[7] ; 
    AI <= (L_ACCDAT[1] | L_ACCDAT[2]) & L_ACCDAT[3] & STATD[2] ; 
    AJ <= (L_ACCDAT[5] | L_ACCDAT[6]) & L_ACCDAT[7] & STATD[5] ; 
  end 

  always @(MULDIV or AD or AE or AF or STATD or CYC)
  begin : misc2
    BD <= AD | AE ; 
    BE <= AD | AF ; 
    BF <= STATD[2] & MULDIV & CYC[1] ; 
  end 

  always @(MULDIV or DAA or ACCADD or LCYC or SFRW or STATD or DIV2CK)
  begin : load_reg_en
    // Enable accumulator load: This may happen at the end of s3p2, s6p2,
    // or alternatively at the end of s5p2 for exchange instructions.
    // The B register may only load at the end of s6p2.
    ACC_EN <= ~DIV2CK & ((STATD[3] & (MULDIV | DAA)) | (STATD[5] & ACCADD[
    8]) | (STATD[6] & (MULDIV | (ACCADD[7] & LCYC) | SFRW[21]))) ; 
    B_REG_EN <= ~DIV2CK & ((STATD[6] & LCYC & MULDIV) | SFRW[20]) ; 
  end 

  always @(STATD or CYC or ACCADD or MULDIV or DIV2CK)
  begin : load_temp_2_en
    // temporary register 2 loads on s2p2 and s5p2.  This happens always in
    // cycle 1 and in higher cycle numbers for selected instructions.
    TEMP2_EN <= ~DIV2CK & ((STATD[2] & (CYC[1] | ACCADD[5] | MULDIV | ACCADD[
    9])) | (STATD[5] & (CYC[1] | ACCADD[5] | MULDIV))) ; 
  end 

  always @(posedge RST or posedge NX1)
  begin : update_registers
    if (RST)
    begin
      L_ACCDAT <= 8'b00000000 ; 
      BREG <= 8'b00000000 ; 
      ACLDAT[9:0] <= 10'b0000000000 ; 
      ACC0 <= 1'b0 ; 
    end
    else
    begin
      // Load the accumulator, B register and temporary register 2 (ACLDAT).
      if (ACC_EN)
      begin
        L_ACCDAT <= LDATAA ; 
      end 
      if (B_REG_EN)
      begin
        BREG <= LDATAD ; 
      end 
      if (TEMP2_EN)
      begin
        ACLDAT[9] <= PSWDAT[7] ; 
        ACLDAT[8] <= PSWDAT[6] ; 
        ACLDAT[7:0] <= LDATAC[7:0] ; 
        ACC0 <= L_ACCDAT[0] ; 
      end 
    end 
  end 

  always @(AG or AH or AI or AJ or L_ACCDAT or RDAT)
  begin : genout
    ACCDAT <= L_ACCDAT ; 
    REGMOD[3:0] <= RDAT[3:0] ; 
    DAAL <= AG | AI ; 
    DAAH <= AH | AJ ; 
    PAR <= L_ACCDAT[0] ^ L_ACCDAT[1] ^ L_ACCDAT[2] ^ L_ACCDAT[3] ^ L_ACCDAT[
    4] ^ L_ACCDAT[5] ^ L_ACCDAT[6] ^ L_ACCDAT[7] ; 
  end 
  //*********************************************************************
endmodule