m3s039bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//m3s039bo Special Function Register Write Strobe Generator
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:06:20 1998
//
// Input file : m3s039bo.vhd
// Design name : m3s039bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s039bo.vhd
//Created on    :       20th Oct 1995
//Purpose       :       Write strobe and load mux  control generator
//Version       :       1.005
//Mod Date      :       2nd April 1998
//Mod History	:	1.005 _e suffix removed from entity names.
//                      1.004 Redundancy removed.
//                      1.003 SFR expansion capability added, address
//                            decoder re-written for legibility.
//                      1.002 Synthesis Fixes
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s008bo.vhd
//Calls to              :None
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s039bo (SFRW, WEP, FA, SFR_LOAD, SFRWE);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //

  output[21:0] SFRW;
  reg[21:0] SFRW;
  output WEP;
  reg WEP;
  input[6:0] FA;
  input SFR_LOAD;
  input SFRWE;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg A000; 
  reg A001; 
  reg A010; 
  reg A011; 
  reg A100; 
  reg A101; 
  reg A111; 
  reg AH0000; 
  reg AH0001; 
  reg AH0010; 
  reg AH0011; 
  reg AH0100; 
  reg AH0110; 
  reg AH1010; 
  reg AH1100; 
  reg AH1110; 
  reg AH1111; 
  reg AH01X1; 

  always @(FA)
  begin : addr_decode1
    // Generate intermediate SFR address decoding
    // Decodes for the lower three data memory address bits.
    A000 <= ~FA[2] & ~FA[1] & ~FA[0] ; 
    A001 <= ~FA[2] & ~FA[1] & FA[0] ; 
    A010 <= ~FA[2] & FA[1] & ~FA[0] ; 
    A011 <= ~FA[2] & FA[1] & FA[0] ; 
    A100 <= FA[2] & ~FA[1] & ~FA[0] ; 
    A101 <= FA[2] & ~FA[1] & FA[0] ; 
    A111 <= FA[2] & FA[1] & FA[0] ; 
    // Decodes for data memory address bits 3 to 6.
    AH0000 <= ~FA[6] & ~FA[5] & ~FA[4] & ~FA[3] ; 
    AH0001 <= ~FA[6] & ~FA[5] & ~FA[4] & FA[3] ; 
    AH0010 <= ~FA[6] & ~FA[5] & FA[4] & ~FA[3] ; 
    AH0011 <= ~FA[6] & ~FA[5] & FA[4] & FA[3] ; 
    AH0100 <= ~FA[6] & FA[5] & ~FA[4] & ~FA[3] ; 
    AH0110 <= ~FA[6] & FA[5] & FA[4] & ~FA[3] ; 
    AH1010 <= FA[6] & ~FA[5] & FA[4] & ~FA[3] ; 
    AH1100 <= FA[6] & FA[5] & ~FA[4] & ~FA[3] ; 
    AH1110 <= FA[6] & FA[5] & FA[4] & ~FA[3] ; 
    AH1111 <= FA[6] & FA[5] & FA[4] & FA[3] ; 
    AH01X1 <= ~FA[6] & FA[5] & FA[3] ; 
  end 

  always @(A000 or A001 or A010 or A011 or A100 or A101 or A111 or AH0000 or 
   AH0001 or AH0010 or AH0011 or AH0100 or AH0110 or AH1010 or AH1100 or 
   AH1110 or AH1111 or AH01X1 or FA or SFRWE or SFR_LOAD)
  begin : sfrout
    // Use address decodes to drive SFR write enables at end of S6P2.
    SFRW[21] <= SFRWE & AH1100 & A000 ; 
    SFRW[20] <= SFRWE & AH1110 & A000 ; 
    SFRW[19] <= SFRWE & AH1111 & A111 ; 
    SFRW[18] <= SFRWE & AH0000 & A111 ; 
    SFRW[17] <= SFRWE & AH1010 & A000 ; 
    SFRW[16] <= SFRWE & AH0000 & A001 ; 
    SFRW[15] <= SFRWE & AH0000 & A011 ; 
    SFRW[14] <= SFRWE & AH0000 & A010 ; 
    SFRW[13] <= SFRWE & AH01X1 & A000 & FA[4] ; 
    SFRW[12] <= SFRWE & AH01X1 & A000 & ~FA[4] ; 
    SFRW[11] <= SFRWE & AH0011 & A001 ; 
    SFRW[10] <= SFRWE & AH0011 & A000 ; 
    SFRW[9] <= SFRWE & AH0001 & A101 ; 
    SFRW[8] <= SFRWE & AH0001 & A100 ; 
    SFRW[7] <= SFRWE & AH0001 & A011 ; 
    SFRW[6] <= SFRWE & AH0001 & A010 ; 
    SFRW[5] <= SFRWE & AH0001 & A001 ; 
    SFRW[4] <= SFRWE & AH0001 & A000 ; 
    SFRW[3] <= SFRWE & AH0110 & A000 ; 
    SFRW[2] <= SFRWE & AH0100 & A000 ; 
    SFRW[1] <= SFRWE & AH0010 & A000 ; 
    SFRW[0] <= SFRWE & AH0000 & A000 ; 
    // Disable interrupts during write to IE or IP
    WEP <= SFR_LOAD & AH01X1 & A000 ; 
  end 
endmodule