m3s015bo.v

another 8051 core porocesssor vhdl source code

        if (LOV0 & (S_EN | (RMW & STATD[6])))
        begin
          TCON[5] <= 1'b1 ; 
        end
        else if (SFRW[4])
        begin
          TCON[5] <= RAMDI[5] ; 
        end 
      end 
      if (!(IACK[3]))
      begin
        TCON[7] <= 1'b0 ; 
      end
      else if (!DIV2CK1)
      begin
        if (LLOV1 & (S_EN | (RMW & STATD[6])))
        begin
          TCON[7] <= 1'b1 ; 
        end
        else if (SFRW[4])
        begin
          TCON[7] <= RAMDI[7] ; 
        end 
      end 
    end  
  end 

  always @(LTCON0 or LTCON1 or INT0 or OLD_INT0)
  begin : selecttcon1
    case (LTCON0)
      1'b0 :
            begin
              TCON[1] <= INT0 | OLD_INT0 ; 
            end
      1'b1 :
            begin
              TCON[1] <= LTCON1 ; 
            end
      default :
            begin
              TCON[1] <= 1'bx ; 
            end
    endcase 
  end 

  always @(LTCON2 or LTCON3 or INT1 or OLD_INT1)
  begin : selecttcon3
    case (LTCON2)
      1'b0 :
            begin
              TCON[3] <= INT1 | OLD_INT1 ; 
            end
      1'b1 :
            begin
              TCON[3] <= LTCON3 ; 
            end
      default :
            begin
              TCON[3] <= 1'bx ; 
            end
    endcase 
  end 

  always @(posedge NX1)
  begin : p3sampler
    // External input sampling flip-flops.  All four port inputs are sampled on S5P2
    if (CLEAR)
    begin
      INT0 <= 1'b0 ; 
      INT1 <= 1'b0 ; 
      T0 <= 1'b0 ; 
      T1 <= 1'b0 ; 
      OLD_INT0 <= 1'b0 ; 
      OLD_INT1 <= 1'b0 ; 
      OLD_T0 <= 1'b0 ; 
      OLD_T1 <= 1'b0 ; 
    end
    else if (!DIV2CK1 & S_EN)
    begin
      INT0 <= ~DI[2] ; 
      INT1 <= ~DI[3] ; 
      T0 <= DI[4] ; 
      T1 <= DI[5] ; 
      OLD_INT0 <= INT0 ; 
      OLD_INT1 <= INT1 ; 
      OLD_T0 <= T0 ; 
      OLD_T1 <= T1 ; 
    end  
  end 

  always @(T0 or T1 or OLD_T0 or OLD_T1)
  begin : set_cnt2
    // External counter input falling edge detectors
    CNT0 <= OLD_T0 & ~T0 ; 
    CNT1 <= OLD_T1 & ~T1 ; 
  end 

  always @(INT0 or INT1 or OLD_INT0 or OLD_INT1)
  begin : tconsetclr
    // External interrupt falling edge detectors
    TCON1SET <= INT0 & ~OLD_INT0 ; 
    TCON3SET <= INT1 & ~OLD_INT1 ; 
  end 

  always @(posedge NX1)
  begin : synch_ov0
    // convert counter timer 0 carry out to overflow
    // Interrupt source is set at timer oveflow (end of S2P2) and cleared at
    // end of S6P2.
    if (T0L_EN)
    begin
      LOV0 <= ILOV0 ; 
    end
    else if (STATE12)
    begin
      LOV0 <= 1'b0 ; 
    end  
  end 

  always @(posedge NX1)
  begin : synch_ov1
    // convert counter timer 1 carry out to overflow
    // Interrupt source is set at timer oveflow (end of S2P2) and cleared at
    // end of S6P2.
    if (OV1_EN)
    begin
      LLOV1 <= ILOV1 ; 
    end
    else if (STATE12)
    begin
      LLOV1 <= 1'b0 ; 
    end  
  end 

  always @(posedge NX2)
  begin : settmod
    if (CLEAR)
    begin
      LTMOD[7:0] <= 8'b00000000 ; 
    end
    else if (SFRW[5])
    begin
      LTMOD[7:0] <= RAMDI[7:0] ; 
    end  
  end 

  always @(LTMOD)
  begin : set_mods
    MODL0 <= ~(LTMOD[0] | LTMOD[1]) ; 
    MODL1 <= ~(LTMOD[4] | LTMOD[5]) ; 
  end 

  always @(T_EN or DIV2CK1)
  begin : timertims
    TIMERS_EN <= T_EN & ~DIV2CK1 ; 
  end 

  always @(LTMOD or TIMERS_EN or T1_MODE3 or CNT0 or CNT1)
  begin : timcntenabs
    // Timer Counters increment on S3P1 regardless of mode.
    // Timer Counter 1 does not count in mode 3.
    COUNTER0_EN <= TIMERS_EN & LTMOD[2] & CNT0 ; 
    COUNTER1_EN <= TIMERS_EN & LTMOD[6] & CNT1 & ~T1_MODE3 ; 
    TIMER0_EN <= TIMERS_EN & ~LTMOD[2] ; 
    TIMER1_EN <= TIMERS_EN & ~LTMOD[6] & ~T1_MODE3 ; 
  end 

  always @(COUNTER0_EN or COUNTER1_EN or TIMER0_EN or TIMER1_EN or TIMERS_EN 
  or 
   T0_MODE3 or SFRW)
  begin : timer_en
    T0L_EN <= COUNTER0_EN | TIMER0_EN | SFRW[6] ; 
    T0H_EN <= (~(T0_MODE3) & (COUNTER0_EN | TIMER0_EN)) | (T0_MODE3 & TIMERS_EN)
    | SFRW[8] ; 
    T1_EN <= COUNTER1_EN | TIMER1_EN | SFRW[7] | SFRW[9] ; 
  end 

  always @(T0H_EN or T1_EN or T0_MODE3)
  begin : overflow1_en
    // MUX for replacing T1_EN with T0H_EN as clock source for overflow
    // register in mode 3.
    OV1_EN <= (T1_EN & ~T0_MODE3) | (T0H_EN & T0_MODE3) ; 
  end 

  always @(LTMOD or T0_MODE3 or LTCON4 or LTCON6 or INT0 or INT1 or COL0 or 
   COL1 or STATD)
  begin : set_nci
    // Define carry inputs to the four 8-bit counters.
    // Mask carry inputs during SFR write window (end STATD(6)).
    CIL0 <= LTCON4 & (~(LTMOD[3]) | ~INT0) & ~STATD[6] ; 
    CIL1 <= LTCON6 & (~(LTMOD[7]) | ~INT1) & ~STATD[6] ; 
    CIH0 <= ((COL0 & ~LTMOD[1]) | (T0_MODE3 & LTCON6)) & ~STATD[6] ; 
    CIH1 <= COL1 & ~LTMOD[5] & ~STATD[6] ; 
  end 

  always @(COH0 or COL0 or COL1 or COH1 or LTMOD or CLEAR or AB or AC)
  begin : set_ilov
    ILOV0 <= ((COH0 & ~LTMOD[1]) | (COL0 & LTMOD[1])) & ~CLEAR ; 
    ILOV1 <= ((COH1 & ~AC) | (COL1 & ~AB) | (COH0 & LTMOD[0] & LTMOD[1]))
    & ~CLEAR ; 
  end 

  always @(SFRW or LTMOD or COL0 or COL1)
  begin : set_low_byte_load
    // Low byte counter load control is OR of SFR write signal and in mode 2
    // the low byte overflow.
    LOAD0 <= SFRW[6] | (LTMOD[1] & ~LTMOD[0] & COL0) ; 
    LOAD1 <= SFRW[7] | (LTMOD[5] & ~LTMOD[4] & COL1) ; 
  end 

  always @(RAMDI or LTHA or LTHB or SFRW)
  begin : set_din
    case (SFRW[6])
      1'b0 :
            begin
              DINA <= LTHA ; 
            end
      1'b1 :
            begin
              DINA <= RAMDI ; 
            end
      default :
            begin
              DINA <= 8'bXXXXXXXX ; 
            end
    endcase 
    case (SFRW[7])
      1'b0 :
            begin
              DINB <= LTHB ; 
            end
      1'b1 :
            begin
              DINB <= RAMDI ; 
            end
      default :
            begin
              DINB <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(LTMOD)
  begin : misc1
    T0_MODE3 <= LTMOD[0] & LTMOD[1] ; 
    T1_MODE3 <= LTMOD[4] & LTMOD[5] ; 
  end 

  always @(LTCON0 or LTCON2 or LTCON4 or LTCON6 or LTHA or LTHB or LTMOD or 
   ILOV1 or S_EN or LLOV1)
  begin : localout
    TCON[0] <= LTCON0 ; 
    TCON[2] <= LTCON2 ; 
    TCON[4] <= LTCON4 ; 
    TCON[6] <= LTCON6 ; 
    THA <= LTHA ; 
    THB <= LTHB ; 
    TMOD[7:0] <= LTMOD[7:0] ; 
    LOV1 <= LLOV1 & S_EN ; 
  end 
  //*********************************************************************
  assign LOGIC0 = 1'b0 ; 
  //*********************************************************************
endmodule