m3s015bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Timer Counters for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//v1.007
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Aug. 10, 1998
// Wed Oct  7 16:49:16 1998
//
// Input file : m3s015bo.vhd
// Design name : m3s015bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s015bo.vhd
//Created on    :       24th Oct 1995
//Purpose       :       Timer Counter for M8051
//Version       :       1.007
//Mod Date      :       7th October 1998
//                      1.007 NINT0/1 sampling time restricted to S5P2
//                      1.006 _e suffix removed from entity names.
//                      1.005 Redundant signals removed, name change,
//                            re-load false path removed.
//                      1.004 Overflow synchronising flip-flops
//                            re-instated, TH0 clock source fix,
//                            timer 1 enable logic,
//                            external interrupt sampling flip-flops,
//                            RMW instructions prevented from erasing
//                            pending timer interrupts.
//                            Level sensitive interrupts now sampled
//                            and registered at end of S5P2.
//                            Sensitivity list revisions.
//			1.003 Idle Mode Power Saving.
//			1.002 Calling file name changed to m8051.vhd
//                      1.001 Original
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :m3s016bo.vhd
//                      :m3s017bo.vhd
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s015bo (LOV1, TCON, TMOD, TLA, TLB, THA, THB, IACK, DI, STATD, RAMDI,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
SFRW, RMW, S_EN, T_EN, STATE12, DIV2CK1, NX1, NX2, CLEAR);

  output LOV1;
  reg LOV1;
  output[7:0] TCON;
  reg[7:0] TCON;
  output[7:0] TMOD;
  reg[7:0] TMOD;
  output[7:0] TLA;
  wire[7:0] TLA;
  output[7:0] TLB;
  wire[7:0] TLB;
  output[7:0] THA;
  reg[7:0] THA;
  output[7:0] THB;
  reg[7:0] THB;
  input[3:0] IACK;
  input[5:2] DI;
  input[6:6] STATD;
  input[7:0] RAMDI;
  input[9:4] SFRW;
  input RMW;
  input S_EN;
  input T_EN;
  input STATE12;
  input DIV2CK1;
  input NX1;
  input NX2;
  input CLEAR;

  //*********************************************************************
  //*********************************************************************
  // Component Definition
  //*********************************************************************
  //8 bit loadable counter with carry out from fifth or eighth bit.
  //*********************************************************************
  //signal definition
  //*********************************************************************
  wire COH0; 
  wire COH1; 
  wire COL0; 
  wire COL1; 
  reg CIH0; 
  reg CIH1; 
  reg CIL0; 
  reg CIL1; 
  reg MODL0; 
  reg MODL1; 
  reg T0L_EN; 
  reg T0H_EN; 
  reg T1_EN; 
  reg OV1_EN; 
  reg CNT0; 
  reg CNT1; 
  reg T0_MODE3; 
  reg T1_MODE3; 
  reg LOAD0; 
  reg LOAD1; 
  reg ILOV0; 
  reg ILOV1; 
  reg LTCON0; 
  reg LTCON1; 
  reg LTCON2; 
  reg LTCON3; 
  reg LTCON4; 
  reg LTCON6; 
  reg TCON1SET; 
  reg TCON3SET; 
  reg AB; 
  reg AC; 
  reg[7:0] LTMOD; 
  wire[7:0] LTHA; 
  wire[7:0] LTHB; 
  reg[7:0] DINA; 
  reg[7:0] DINB; 
  reg COUNTER0_EN; 
  reg COUNTER1_EN; 
  reg TIMER0_EN; 
  reg TIMER1_EN; 
  reg TIMERS_EN; 
  reg LOV0; // synchronised timer overflow registers
  reg LLOV1; // synchronised timer overflow registers
  reg INT0; // sampled external interrupt inputs
  reg INT1; // sampled external interrupt inputs
  reg OLD_INT0; // external interrupt memories
  reg OLD_INT1; // external interrupt memories
  reg T0; // sampled counter inputs
  reg T1; // sampled counter inputs
  reg OLD_T0; // sampled counter inputs
  reg OLD_T1; // sampled counter inputs
  wire LOGIC0; 
  //*********************************************************************
  //*********************************************************************
  //port mapping
  //*********************************************************************
  //*********************************************************************
  //Timer zero high byte
  m3s016bo U1 (.CO(COH0), .CNT(LTHA), .MODE0(LOGIC0), .LD(SFRW[8]), .CI(CIH0),
  .CLEAR(CLEAR), .COUNT_EN(T0H_EN), .NX1(NX1), .DIN(RAMDI)); 
  //*********************************************************************
  //Timer one high byte
  m3s016bo U2 (.CO(COH1), .CNT(LTHB), .MODE0(LOGIC0), .LD(SFRW[9]), .CI(CIH1),
  .CLEAR(CLEAR), .COUNT_EN(T1_EN), .NX1(NX1), .DIN(RAMDI)); 
  //*********************************************************************
  // Timer zero low byte
  m3s016bo U3 (.CO(COL0), .CNT(TLA), .MODE0(MODL0), .LD(LOAD0), .CI(CIL0),
  .CLEAR(CLEAR), .COUNT_EN(T0L_EN), .NX1(NX1), .DIN(DINA)); 
  //*********************************************************************
  // Timer one low byte
  m3s016bo U4 (.CO(COL1), .CNT(TLB), .MODE0(MODL1), .LD(LOAD1), .CI(CIL1),
  .CLEAR(CLEAR), .COUNT_EN(T1_EN), .NX1(NX1), .DIN(DINB)); 

  always @(posedge NX2)
  begin : tconeven
    if (CLEAR)
    begin
      LTCON0 <= 1'b0 ; 
      LTCON2 <= 1'b0 ; 
      LTCON4 <= 1'b0 ; 
      LTCON6 <= 1'b0 ; 
    end
    else if (SFRW[4])
    begin
      LTCON0 <= RAMDI[0] ; 
      LTCON2 <= RAMDI[2] ; 
      LTCON4 <= RAMDI[4] ; 
      LTCON6 <= RAMDI[6] ; 
    end  
  end 

  always @(LTMOD)
  begin : gen1
    AB <= LTMOD[4] | (LTMOD[0] & LTMOD[1]) | ~LTMOD[5] ; 
    AC <= LTMOD[5] | (LTMOD[0] & LTMOD[1]) ; 
  end 

  always @(posedge NX1)
  begin : tconodd
    if (CLEAR)
    begin
      LTCON1 <= 1'b0 ; 
      LTCON3 <= 1'b0 ; 
      TCON[5] <= 1'b0 ; 
      TCON[7] <= 1'b0 ; 
    end
    else
    begin
      if (!(IACK[0]))
      begin
        LTCON1 <= 1'b0 ; 
      end
      else if (TCON1SET)
      begin
        LTCON1 <= 1'b1 ; 
      end
      else if (SFRW[4])
      begin
        LTCON1 <= RAMDI[1] ; 
      end 
      // TCON odd bits may be set at S5P2 by interrupt sources
      // Interrupts may be overwritten by direct register load instructions,
      // but not by read-modify-write instructions.
      if (!(IACK[2]))
      begin
        LTCON3 <= 1'b0 ; 
      end
      else if (TCON3SET)
      begin
        LTCON3 <= 1'b1 ; 
      end
      else if (SFRW[4])
      begin
        LTCON3 <= RAMDI[3] ; 
      end 
      if (!(IACK[1]))
      begin
        TCON[5] <= 1'b0 ; 
      end
      else if (!DIV2CK1)
      begin