m3s020bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Miscellaneous Special Function Registers for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
//v1.007
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:38 1998
//
// Input file : m3s020bo.vhd
// Design name : m3s020bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s020bo.vhd
//Created on    :       29th Nov 1995
//Purpose       :       misc registers inc stack pointer for M8051
//Version       :       1.007
//Mod Date      :       2nd April 1998
//Mod History	:       1.007 _e suffix removed from entity names.
//                      1.006 STATD(7-12) and DIV2CK1 removed
//                      1.005 Parity flag write timing corrected.
//                      1.004 ECN 878: Carry updated in cycle 2 for CJNE
//                            instructions, redundancy removed from
//                            PSWDAT(7) and PSWC.  Sensitivity list
//                            revisions.  XROM moved to m3s010bo.
//                      1.003 Idle Mode Power Saving
//			1.002 Calling file name changed to m8051
//                      1.001 Original
//
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :m3s014bo.vhd
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s020bo (RESINT, SP, PCON, PSWDAT, MSIZ, CO, ACO, OV, PAR, DAA, CJNE,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
OPLOAD, MULDIV, INTA, LCYC, DIV2CK2, CLEAR, RST, STATE12, NX1, NX2, CYC, 
PSWC, SPC, STATD, RAMDI, SFRW);

  output RESINT;
  reg RESINT;
  output[7:0] SP;
  wire[7:0] SP;
  output[7:0] PCON;
  reg[7:0] PCON;
  output[7:0] PSWDAT;
  reg[7:0] PSWDAT;
  output[7:0] MSIZ;
  reg[7:0] MSIZ;
  input CO;
  input ACO;
  input OV;
  input PAR;
  input DAA;
  input CJNE;
  input OPLOAD;
  input MULDIV;
  input INTA;
  input LCYC;
  input DIV2CK2;
  input CLEAR;
  input RST;
  input STATE12;
  input NX1;
  input NX2;
  input[2:1] CYC;
  input[2:0] PSWC;
  input[3:0] SPC;
  input[6:1] STATD;
  input[7:0] RAMDI;
  input[19:16] SFRW;

  //*********************************************************************
  //*********************************************************************
  // Component Definitions
  //*********************************************************************
  //Stack Pointer
  //*********************************************************************
  //*********************************************************************
  //signal definition
  //*********************************************************************
  reg L_RESINT; 
  reg AA; 
  reg ENAB; 
  reg[7:0] L_MSIZ; 
  reg[1:0] L_PCON; 
  //*********************************************************************
  //*********************************************************************
  //port mapping
  //*********************************************************************
  //*********************************************************************
  m3s014bo U1 (.SP(SP), .RAMDI(RAMDI), .SPC(SPC[1:0]), .SFRW(SFRW[16:16]),
  .DIV2CK(DIV2CK2), .NX1(NX2), .CLEAR(CLEAR), .ENAB(ENAB)); 

  always @(STATD or SPC)
  begin : misc1
    AA <= (STATD[2] & SPC[1]) | (STATD[5] & SPC[0]) ; 
  end 

  always @(AA or CYC or SPC or L_RESINT or SFRW)
  begin : setenab
    ENAB <= ((AA & ~L_RESINT) & ((SPC[2] & CYC[1]) | (SPC[3] & CYC[2]))) |
    SFRW[16] ; 
  end 

  always @(posedge NX2 or posedge RST)
  begin : setpconhi
    if (RST)
    begin
      PCON[7:2] <= 6'b000000 ; 
    end
    else
    begin
      if (SFRW[18])
      begin
        PCON[7:2] <= RAMDI[7:2] ; 
      end 
    end 
  end 

  always @(posedge NX1 or posedge RST)
  begin : setpconlo
    if (RST)
    begin
      L_PCON[1:0] <= 2'b00 ; 
    end
    else
    begin
      if ((STATE12 & INTA))
      begin
        L_PCON[1:0] <= 2'b00 ; 
      end
      else if (SFRW[18])
      begin
        L_PCON[1:0] <= RAMDI[1:0] ; 
      end 
    end 
  end 

  always @(posedge NX2)
  begin : setpsw
    if (CLEAR)
    begin
      PSWDAT[7:0] <= 8'b00000000 ; 
    end
    else
    begin
      if (SFRW[17])
      begin
        PSWDAT[1] <= RAMDI[1] ; 
        PSWDAT[5:3] <= RAMDI[5:3] ; 
      end 
      if (STATD[6] & LCYC & ~DIV2CK2)
      begin
        if (SFRW[17])
        begin
          PSWDAT[2] <= RAMDI[2] ; 
          PSWDAT[6] <= RAMDI[6] ; 
          PSWDAT[7] <= RAMDI[7] ; 
        end
        else
        begin
          if (PSWC[0])
          begin
            PSWDAT[2] <= OV ; 
          end 
          if (PSWC[1])
          begin
            PSWDAT[6] <= ACO ; 
          end 
          if (PSWC[2])
          begin
            PSWDAT[7] <= (CO & ~MULDIV) ; 
          end 
        end 
      end 
      if (STATD[1] & DIV2CK2 & CYC[1])
      begin
        PSWDAT[0] <= PAR ; 
      end 
      if (STATD[3] & ~DIV2CK2 & (DAA | (CYC[2] & CJNE)))
      begin
        PSWDAT[7] <= CO ; 
      end 
    end  
  end 

  always @(posedge NX2)
  begin : setmsiz
    if (CLEAR)
    begin
      L_MSIZ <= 8'b00001111 ; 
    end
    else if (SFRW[19])
    begin
      L_MSIZ <= RAMDI ; 
    end  
  end 

  always @(L_RESINT or L_MSIZ or L_PCON)
  begin : localout
    RESINT <= L_RESINT ; 
    MSIZ <= L_MSIZ ; 
    PCON[1:0] <= L_PCON ; 
  end 

  always @(posedge NX2)
  begin : setresint
    if (CLEAR)
    begin
      L_RESINT <= 1'b1 ; 
    end
    else if (OPLOAD)
    begin
      L_RESINT <= 1'b0 ; 
    end  
  end 
  //*********************************************************************
endmodule