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📄 m3s002bo.v

📁 another 8051 core porocesssor vhdl source code
💻 V
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//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      ////M8051 ALU element//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights reserved.//v1.003//////////////////////////////////////////////////////////////////////////////////// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998// Thu Jul  9 22:04:36 1998//// Input file : m3s002bo.vhd// Design name : m3s002bo// Author : // Company : Mentor Graphics - Inventra//// Description : ////////////////////////////////////////////////////////////////////////////////////////*********************************************************************//%W% %G% SCCS Version Control//File	        :       m3s002bo.vhd//Created on    :       1st Oct 1995//Purpose       :       M8051 Megamacro ALU element //Version       :       1.003//Mod Date      :       2nd April 1998//Mod History	:	1.003 _e suffix removed from entity names.//                      1.002 Comments updated.////*********************************************************************//Hierarchy record      ://Called by             :m3s003bo.vhd//Calls to              :None//*********************************************************************//*********************************************************************//Entity Definition//*********************************************************************module m3s002bo (P, CO, ALUC, A, B);//*******************************************************************       ////IMPORTANT NOTICE                                                          ////================                                                          ////Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  ////This file and associated deliverables are the trade secrets,              ////confidential information and copyrighted works of Mentor Graphics         ////Corporation and its licensors and are subject to your license agreement   ////with Mentor Graphics Corporation.                                         ////                                                                          ////Use of these deliverables for the purpose of making silicon from an IC    ////design is limited to the terms and conditions of your license agreement   ////with Mentor Graphics If you have further questions please contact Mentor  ////Graphics Customer Support.                                                ////                                                                          ////This Mentor Graphics core (m8051 v1999.120) was extracted on              ////workstation hostid _hostid_ Inventra                                      //  output P;  reg P;  output CO;  reg CO;  input[5:0] ALUC;  input A;  input B;  //*********************************************************************  reg AA;   reg AB;   reg AC;   reg AD;   reg AE;   reg AF;   always @(A or B or ALUC)  begin : misc1    AA <= ~A & ~B & ALUC[0] ;     AB <= ~A & B & ALUC[1] ;     AC <= A & B & ALUC[2] ;     AD <= A & ~B & ALUC[3] ;     AE <= A & B & ALUC[4] ;     AF <= A & ~B & ALUC[5] ;   end   always @(AA or AB or AC or AD or AE or AF)  begin : misc2    P <= AA | AB | AC | AD ;     CO <= AE | AF ;   end   //*********************************************************************  //*********************************************************************endmodule

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