m3s006bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// ALU Temporary Register Number 1 for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved
//v1.005
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:04:55 1998
//
// Input file : m3s006bo.vhd
// Design name : m3s006bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s006bo.vhd
//Created on    :       8th October 1995
//Purpose       :       ALU Temporary Register 1
//Version       :       1.005
//Mod Date      :       2nd April 1998
//Mod History	:       1.005 _e suffix removed from entity names.
//                      1.004 Timing Revision and
//                            unused signals in sensitivity lists.
//                      1.003-OPH and OPL changed to DPH and DPL
//                      1.002-Calling file name changed to m8051.vhd
//                      1.001(Original)
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//-------------------------------------------------
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s006bo (TMPDAT, PROGRAM_COUNT, RDAT, IMMDAT, DPH, DPL, BREG, TMPADD,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
CODAT, CYC, STATD, LOGDI, DIV2CK, NX1, RST);

  output[7:0] TMPDAT;
  reg[7:0] TMPDAT;
  input[15:0] PROGRAM_COUNT;
  input[7:0] RDAT;
  input[7:0] IMMDAT;
  input[7:0] DPH;
  input[7:0] DPL;
  input[7:0] BREG;
  input[3:0] TMPADD;
  input[2:0] CODAT;
  input[1:1] CYC;
  input[5:2] STATD;
  input LOGDI;
  input DIV2CK;
  input NX1;
  input RST;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg AA; 
  reg TEMP1_EN; 
  reg[7:0] LDATAA; 
  reg[7:0] LDATAB; 
  reg[7:0] TEMP1_DATA; 
  reg[1:0] MUXVECT1; 

  always @(CYC or LOGDI)
  begin : misc1
    AA <= CYC[1] | LOGDI ; 
  end 

  always @(AA or STATD or CYC)
  begin : gencon
    TEMP1_EN <= (AA & STATD[2]) | (CYC[1] & STATD[5]) ; 
  end 

  always @(TMPADD or STATD)
  begin : setmuxvect1
    MUXVECT1 <= {TMPADD[3], STATD[5]} ; 
  end 

  always @(DPL or DPH or PROGRAM_COUNT or MUXVECT1)
  begin : set_abus
    // select source for 16-bit address arithmetic
    case (MUXVECT1)
      2'b00 :
            begin
              LDATAA <= DPL ; 
            end
      2'b01 :
            begin
              LDATAA <= DPH ; 
            end
      2'b10 :
            begin
              LDATAA <= PROGRAM_COUNT[7:0] ; 
            end
      2'b11 :
            begin
              LDATAA <= PROGRAM_COUNT[15:8] ; 
            end
      default :
            begin
              LDATAA <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(BREG or LDATAA or TMPADD)
  begin : set_bbus
    case (TMPADD[2])
      1'b0 :
            begin
              LDATAB <= BREG ; 
            end
      1'b1 :
            begin
              LDATAB <= LDATAA ; 
            end
      default :
            begin
              LDATAB <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(CODAT or IMMDAT or RDAT or LDATAB or TMPADD)
  begin : set_ALU_constant
    // generate ALU input constants for increment, decrement and decimal
    // adjust instructions.
    case (TMPADD[1:0])
      2'b00 :
            begin
              TEMP1_DATA[1:0] <= CODAT[1:0] ; 
              TEMP1_DATA[2] <= CODAT[1] ; 
              TEMP1_DATA[4:3] <= 2'b00 ; 
              TEMP1_DATA[5] <= CODAT[2] ; 
              TEMP1_DATA[6] <= CODAT[2] ; 
              TEMP1_DATA[7] <= 1'b0 ; 
            end
      2'b01 :
            begin
              TEMP1_DATA <= IMMDAT ; 
            end
      2'b10 :
            begin
              TEMP1_DATA <= RDAT ; 
            end
      2'b11 :
            begin
              TEMP1_DATA <= LDATAB ; 
            end
      default :
            begin
              TEMP1_DATA <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(posedge NX1 or posedge RST)
  begin : tmpout
    if (RST)
    begin
      TMPDAT <= 8'b00000000 ; 
    end
    else
    begin
      if (TEMP1_EN & ~DIV2CK)
      begin
        TMPDAT <= TEMP1_DATA ; 
      end 
    end 
  end 
  //*********************************************************************
endmodule