m3s014bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
// Stack Pointer for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.
//v1.003
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:17 1998
//
// Input file : m3s014bo.vhd
// Design name : m3s014bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s014bo.vhd
//Created on    :       28th November 1995
//Purpose       :       Stack Pointer sub-block of m8051
//Version       :       1.003
//Mod Date      :       2nd April 1998
//Mod History	:	1.003 _e suffix removed from entity names.
//                      1.002 Sensitivity List Revisions.
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m3s020bo.vhd
//Calls to              :None
//                      :
//                      :
//                      :
//-------------------------------------------------
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s014bo (SP, RAMDI, SPC, SFRW, DIV2CK, NX1, CLEAR, ENAB);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //

  output[7:0] SP;
  reg[7:0] SP;
  input[7:0] RAMDI;
  input[1:0] SPC;
  input[16:16] SFRW;
  input DIV2CK;
  input NX1;
  input CLEAR;
  input ENAB;

  //*********************************************************************
  //*********************************************************************
  //Signal definitions
  //*********************************************************************
  reg[7:0] L_SP; 
  reg[7:0] LOCALA; 
  reg[7:0] LOCALB; 
  reg[6:0] CD; 
  reg[6:0] CU; 

  always @(L_SP)
  begin : localout
    SP <= L_SP ; 
  end 

  always @(SFRW or RAMDI or LOCALB)
  begin : muxlocala
    case (SFRW[16])
      1'b0 :
            begin
              LOCALA <= LOCALB ; 
            end
      1'b1 :
            begin
              LOCALA <= RAMDI ; 
            end
      default :
            begin
              LOCALA <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(posedge NX1)
  begin : setsp
    if (CLEAR)
    begin
      L_SP <= 8'b00000111 ; 
    end
    else if ((ENAB & ~DIV2CK))
    begin
      L_SP <= LOCALA ; 
    end  
  end 

  always @(SPC or L_SP or CU or CD)
  begin : setlocalb
    LOCALB[0] <= (SPC[0] | SPC[1]) ^ L_SP[0] ; 
    LOCALB[1] <= (CU[0] | CD[0]) ^ L_SP[1] ; 
    LOCALB[2] <= (CU[1] | CD[1]) ^ L_SP[2] ; 
    LOCALB[3] <= (CU[2] | CD[2]) ^ L_SP[3] ; 
    LOCALB[4] <= (CU[3] | CD[3]) ^ L_SP[4] ; 
    LOCALB[5] <= (CU[4] | CD[4]) ^ L_SP[5] ; 
    LOCALB[6] <= (CU[5] | CD[5]) ^ L_SP[6] ; 
    LOCALB[7] <= (CU[6] | CD[6]) ^ L_SP[7] ; 
  end 

  always @(SPC or L_SP or CU)
  begin : setcueven
    CU[0] <= SPC[1] & L_SP[0] ; 
    CU[2] <= CU[1] & L_SP[2] ; 
    CU[4] <= CU[3] & L_SP[4] ; 
    CU[6] <= CU[5] & L_SP[6] ; 
  end 

  always @(CU or L_SP)
  begin : setcuodd
    CU[1] <= CU[0] & L_SP[1] ; 
    CU[3] <= CU[2] & L_SP[3] ; 
    CU[5] <= CU[4] & L_SP[5] ; 
  end 

  always @(SPC or L_SP or CD)
  begin : setcdeven
    CD[0] <= SPC[0] & ~L_SP[0] ; 
    CD[2] <= CD[1] & ~L_SP[2] ; 
    CD[4] <= CD[3] & ~L_SP[4] ; 
    CD[6] <= CD[5] & ~L_SP[6] ; 
  end 

  always @(CD or L_SP)
  begin : setcdodd
    CD[1] <= CD[0] & ~L_SP[1] ; 
    CD[3] <= CD[2] & ~L_SP[3] ; 
    CD[5] <= CD[4] & ~L_SP[5] ; 
  end 
  //*********************************************************************
endmodule