m3s018bo.v

another 8051 core porocesssor vhdl source code

  always @(posedge NX2)
  begin : setpodmen
    if (!DIV2CK)
    begin
      if ((STATD[4] & CYC[1] & MOVX[0]))
      begin
        PODMEN <= 1'b1 ; 
      end
      else if ((STATD[4] & CYC[2]) | CLEAR | (MOVX[4] & STATD[5] & EXTDAT))
      begin
        PODMEN <= 1'b0 ; 
      end 
    end  
  end 

  always @(posedge NX2)
  begin : setaddmen
    if (CLEAR)
    begin
      P0DADD <= 1'b0 ; 
    end
    else if (!DIV2CK)
    begin
      if ((STATD[4] & CYC[1] & MOVX[0]))
      begin
        P0DADD <= 1'b1 ; 
      end 
    end
    else if (DIV2CK)
    begin
      if ((STATD[6]))
      begin
        P0DADD <= 1'b0 ; 
      end 
    end  
  end 

  always @(posedge NX2)
  begin : latportin
    if (!DIV2CK)
    begin
      if (STATD[4])
      begin
        LAI_IN <= AI ; 
        LBI_IN <= BI ; 
        LCI_IN <= CI ; 
        LDI_IN <= DI ; 
      end 
    end  
  end 

  always @(posedge NX1 or posedge RST)
  begin : set_hlt
    if (RST)
    begin
      IDLE <= 1'b0 ; 
    end
    else
    begin
      IDLE <= PCON[0] ; 
    end 
  end 

  always @(NQEN or L_EXPMEM or IDLE or MOVX or PORT1_SFR or L_OC or L_OD)
  begin : setouts
    NPSEN <= IDLE | NQEN | ~L_EXPMEM ; 
    MOEI <= ~(L_EXPMEM | NQEN) ; 
    EXPMEM <= L_EXPMEM ; 
    OB <= PORT1_SFR ; 
    OC <= L_OC ; 
    OD <= L_OD ; 
  end 

  always @(QALE or IDLE)
  begin : aleout
    ALE <= IDLE | QALE ; 
  end 

  always @(posedge NX2 or posedge RST)
  begin : setqen
    if (RST)
    begin
      NQEN <= 1'b1 ; 
    end
    else
    begin
      if (!DIV2CK)
      begin
        if ((STATD[5] & ~(CYC[1] & MOVX[0])) | (STATD[2] & ~CLEAR & ~(CYC[
        2] & MOVX[0])))
        begin
          NQEN <= 1'b0 ; 
        end 
      end
      else
      begin
        if (STATD[1] | STATD[4])
        begin
          NQEN <= 1'b1 ; 
        end 
      end 
    end 
  end 

  always @(MOVX or EXTDAT or EXT_PROG_EN or RST)
  begin : setselc
    SELC <= (MOVX[2] & EXTDAT) | (EXT_PROG_EN & ~EXTDAT & ~RST) ; 
  end 

  always @(posedge NX2)
  begin : stretch_movx
    // Extend MOVX write timing on Port 0 by one clock period for exact
    // compatibility with discrete devices.
    EXTEND_MOVX <= STATD[4] & MOVX[3] ;  
  end 

  always @(EXTDAT or EXTEND_MOVX or EXT_PROG_EN or P0DADD or MOVX or CYC)
  begin : setselmuxoa
    // Port 0 output data source control.
    // Concatenate MUX select inputs for benefit of case syntax.
    // Default condition is 110, i.e. output port 0 SFR contents.
    SELA[2:0] <= {((EXTEND_MOVX & CYC[2]) | ~EXTDAT), ((EXTDAT | ~EXT_PROG_EN)
    & ~EXTEND_MOVX & ~P0DADD), MOVX[1]} ; 
  end 

  always @(SELA or DPL or FA or ACCDAT or PROGRAM_ADDR or PORT0_SFR)
  begin : muxoa
    // Port 0 output data source multiplexer
    case (SELA[2:0])
      3'b000 :
            begin
              OAI <= DPL ; 
            end
      3'b001 :
            begin
              OAI <= FA ; 
            end
      3'b010 :
            begin
              OAI <= ACCDAT ; 
            end
      3'b011 :
            begin
              OAI <= ACCDAT ; 
            end
      3'b100 :
            begin
              OAI <= PROGRAM_ADDR[7:0] ; 
            end
      3'b101 :
            begin
              OAI <= PROGRAM_ADDR[7:0] ; 
            end
      3'b110 :
            begin
              OAI <= PORT0_SFR ; 
            end
      3'b111 :
            begin
              OAI <= PORT0_SFR ; 
            end
      default :
            begin
              OAI <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(SELC or PORT2_SFR or LOCALE)
  begin : muxoc
    case (SELC)
      1'b0 :
            begin
              L_OC <= PORT2_SFR ; 
            end
      1'b1 :
            begin
              L_OC <= LOCALE ; 
            end
      default :
            begin
              L_OC <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(RXDO or TXDO or NWR or NRD or PORT3_SFR)
  begin : setodrest
    // Wire-OR alternate function outputs onto port 3 output pins.
    L_OD[0] <= PORT3_SFR[0] & RXDO ; 
    L_OD[1] <= PORT3_SFR[1] & TXDO ; 
    L_OD[2] <= PORT3_SFR[2] ; 
    L_OD[3] <= PORT3_SFR[3] ; 
    L_OD[4] <= PORT3_SFR[4] ; 
    L_OD[5] <= PORT3_SFR[5] ; 
    L_OD[6] <= PORT3_SFR[6] & NWR ; 
    L_OD[7] <= PORT3_SFR[7] & NRD ; 
  end 

  always @(posedge NX2)
  begin : movx_strobes
    if (!DIV2CK)
    begin
      if (STATD[3] | CLEAR)
      begin
        NWR <= 1'b1 ; 
        NRD <= 1'b1 ; 
      end
      else if ((STATD[6] & CYC[1]))
      begin
        NWR <= ~MOVX[3] ; 
        NRD <= ~MOVX[4] ; 
      end 
    end  
  end 

  always @(AEEN or PORT0_SFR)
  begin : setae
    if (AEEN)
    begin
      AE <= 8'b00000000 ; 
    end
    else
    begin
      AE <= PORT0_SFR ; 
    end 
  end 

  always @(posedge NX2 or posedge RST)
  begin : setdelays
    if (RST)
    begin
      PORT1_DEL <= 8'b11111111 ; 
      PORT2_DEL <= 8'b11111111 ; 
      PORT3_DEL <= 8'b11111111 ; 
    end
    else
    begin
      // delay switch off of drive enables on ports one to three by two clock periods.
      if (!DIV2CK)
      begin
        PORT1_DEL <= PORT1_SFR ; 
        PORT2_DEL <= L_OC ; 
        PORT3_DEL <= L_OD ; 
      end 
    end 
  end 

  always @(PORT1_SFR or PORT1_DEL)
  begin : setbe
    BE[0] <= PORT1_SFR[0] & PORT1_DEL[0] ; 
    BE[1] <= PORT1_SFR[1] & PORT1_DEL[1] ; 
    BE[2] <= PORT1_SFR[2] & PORT1_DEL[2] ; 
    BE[3] <= PORT1_SFR[3] & PORT1_DEL[3] ; 
    BE[4] <= PORT1_SFR[4] & PORT1_DEL[4] ; 
    BE[5] <= PORT1_SFR[5] & PORT1_DEL[5] ; 
    BE[6] <= PORT1_SFR[6] & PORT1_DEL[6] ; 
    BE[7] <= PORT1_SFR[7] & PORT1_DEL[7] ; 
  end 

  always @(L_OC or PORT2_DEL or SELC)
  begin : setce
    CE[0] <= L_OC[0] & PORT2_DEL[0] & ~SELC ; 
    CE[1] <= L_OC[1] & PORT2_DEL[1] & ~SELC ; 
    CE[2] <= L_OC[2] & PORT2_DEL[2] & ~SELC ; 
    CE[3] <= L_OC[3] & PORT2_DEL[3] & ~SELC ; 
    CE[4] <= L_OC[4] & PORT2_DEL[4] & ~SELC ; 
    CE[5] <= L_OC[5] & PORT2_DEL[5] & ~SELC ; 
    CE[6] <= L_OC[6] & PORT2_DEL[6] & ~SELC ; 
    CE[7] <= L_OC[7] & PORT2_DEL[7] & ~SELC ; 
  end 

  always @(L_OD or PORT3_DEL)
  begin : setde
    DE[0] <= L_OD[0] & PORT3_DEL[0] ; 
    DE[1] <= L_OD[1] & PORT3_DEL[1] ; 
    DE[2] <= L_OD[2] & PORT3_DEL[2] ; 
    DE[3] <= L_OD[3] & PORT3_DEL[3] ; 
    DE[4] <= L_OD[4] & PORT3_DEL[4] ; 
    DE[5] <= L_OD[5] & PORT3_DEL[5] ; 
    DE[6] <= L_OD[6] & PORT3_DEL[6] ; 
    DE[7] <= L_OD[7] & PORT3_DEL[7] ; 
  end 

  always @(RMW or LAI_IN or PORT0_SFR or LBI_IN or PORT1_SFR or LCI_IN or 
   PORT2_SFR or LDI_IN or PORT3_SFR)
  begin : muxportsin
    // PORT SFR read back MUX:  Port pin values are read unless the 
    // instruction is a read modify write operation in which case the port
    // SFR value is used. 
    case (RMW)
      1'b0 :
            begin
              PORTA <= LAI_IN ; 
              PORTB <= LBI_IN ; 
              PORTC <= LCI_IN ; 
              PORTD <= LDI_IN ; 
            end
      1'b1 :
            begin
              PORTA <= PORT0_SFR ; 
              PORTB <= PORT1_SFR ; 
              PORTC <= PORT2_SFR ; 
              PORTD <= PORT3_SFR ; 
            end
      default :
            begin
              PORTA <= 8'bXXXXXXXX ; 
              PORTB <= 8'bXXXXXXXX ; 
              PORTC <= 8'bXXXXXXXX ; 
              PORTD <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 
  //********************************************************************* 
endmodule