m3s018bo.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//Port Controller and Registers for M8051
//Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.
//v1.011
////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.0_11 Beta C April 24, 1998
// Thu Jul  9 22:05:31 1998
//
// Input file : m3s018bo.vhd
// Design name : m3s018bo
// Author : 
// Company : Mentor Graphics - Inventra
//
// Description : 
//
//
////////////////////////////////////////////////////////////////////////////////
//
//*********************************************************************
//%W% %G% SCCS Version Control
//File	        :       m3s018bo.vhd
//Created on    :       17th Nov 1995
//Purpose       :       Port Control for M8051
//Version       :       1.011
//Mod Date      :       2nd April 1998
//Mod History	:       1.011 Port 2 output drive enable delay register
//                            modified to update unconditionally at the end
//                            of phase two.
//                            _e suffix removed from entity names.
//                      1.010 Port 0 output MUX controls re-written.
//                            Redundant signals removed.
//                      1.009 Name changes and sensitivity list
//                            revisions.
//                            Program address bus revisions.
//                      1.008 ECN 878: revised SFR writeback time.
//                            SFR write time moved to end of S6P2 and
//                            redundant SFR relay flip-flops deleted.
//                            No external timing change results.
//                            EXT_PROG_EN moved to m3s010bo.
//                      1.007 Port initialisation during reset
//                      1.006 Idle Mode Power Saving
//                      1.005 Change for reset compatibility and
//                            OPH and OPL changed to DPH and DPL
//                            ECN 865 Fix for external idle mode;
//                      1.004 Fix to match dummy address fetches
//                      1.003 ECN 837 Fix for movc high byte 
//                      1.002 Calling file name changed to m8051.vhd
//                      1.001 Original
//
//
//*********************************************************************
//Hierarchy record      :
//Called by             :m8051.vhd
//                      :
//                      :
//Calls to              :None
//                      :
//*********************************************************************
//*********************************************************************
//Entity Definition
//*********************************************************************
module m3s018bo (ALE, NPSEN, MOEI, EXPMEM, OAI, OB, OC, OD, AE, BE, CE, DE,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
PORTA, PORTB, PORTC, PORTD, PROGRAM_ADDR, AI, BI, CI, DI, RAMDI, DPL, DPH,
ACCDAT, FA, STATD, MOVX, SFRW, CYC, PCON, XROM, EXT_PROG_EN, NEA, RXDO, TXDO,
RMW, DIV2CK, NX1, NX2, CLEAR, RST, DLMR);

  output ALE;
  reg ALE;
  output NPSEN;
  reg NPSEN;
  output MOEI;
  reg MOEI;
  output EXPMEM;
  reg EXPMEM;
  output[7:0] OAI;
  reg[7:0] OAI;
  output[7:0] OB;
  reg[7:0] OB;
  output[7:0] OC;
  reg[7:0] OC;
  output[7:0] OD;
  reg[7:0] OD;
  output[7:0] AE;
  reg[7:0] AE;
  output[7:0] BE;
  reg[7:0] BE;
  output[7:0] CE;
  reg[7:0] CE;
  output[7:0] DE;
  reg[7:0] DE;
  output[7:0] PORTA;
  reg[7:0] PORTA;
  output[7:0] PORTB;
  reg[7:0] PORTB;
  output[7:0] PORTC;
  reg[7:0] PORTC;
  output[7:0] PORTD;
  reg[7:0] PORTD;
  input[15:0] PROGRAM_ADDR;
  input[7:0] AI;
  input[7:0] BI;
  input[7:0] CI;
  input[7:0] DI;
  input[7:0] RAMDI;
  input[7:0] DPL;
  input[7:0] DPH;
  input[7:0] ACCDAT;
  input[7:0] FA;
  input[6:1] STATD;
  input[4:0] MOVX;
  input[3:0] SFRW;
  input[2:1] CYC;
  input[0:0] PCON;
  input XROM;
  input EXT_PROG_EN;
  input NEA;
  input RXDO;
  input TXDO;
  input RMW;
  input DIV2CK;
  input NX1;
  input NX2;
  input CLEAR;
  input RST;
  input DLMR;

  //*********************************************************************
  //*********************************************************************
  //signal definition
  //*********************************************************************
  reg AA; 
  reg L_EXPMEM; 
  reg POPMEN; 
  reg PODMEN; 
  reg P0DADD; 
  reg AEEN; 
  reg EXTDAT; 
  reg IDLE; 
  reg QALE; 
  reg NQEN; 
  reg NRD; 
  reg NWR; 
  reg SELC; 
  reg EXTEND_MOVX; 
  reg[7:0] PORT1_DEL; 
  reg[7:0] LOCALE; 
  reg[7:0] PORT2_DEL; 
  reg[7:0] PORT3_DEL; 
  reg[7:0] PORT0_SFR; 
  reg[7:0] PORT1_SFR; 
  reg[7:0] PORT2_SFR; 
  reg[7:0] PORT3_SFR; 
  reg[7:0] L_OC; 
  reg[7:0] L_OD; 
  reg[7:0] LAI_IN; 
  reg[7:0] LBI_IN; 
  reg[7:0] LCI_IN; 
  reg[7:0] LDI_IN; 
  reg[2:0] SELA; 

  always @(STATD or MOVX or CYC)
  begin : misc1
    AA <= STATD[3] | (STATD[6] & ~(MOVX[0] & CYC[2])) ; 
  end 

  always @(PODMEN or POPMEN or DLMR)
  begin : misc2
    AEEN <= PODMEN | POPMEN | DLMR ; 
  end 

  always @(posedge NX2 or posedge RST)
  begin : misc4
    if (RST)
    begin
      L_EXPMEM <= 1'b0 ; 
    end
    else
    begin
      if (DIV2CK)
      begin
        L_EXPMEM <= EXT_PROG_EN ; 
      end 
    end 
  end 

  always @(posedge NX2 or posedge RST)
  begin : setale
    if (RST)
    begin
      QALE <= 1'b1 ; 
    end
    else
    begin
      // ALE runs continously regardless of whether program memory read is
      // internal or external.  Ale is only suspended by MOVX instructions.
      if (DIV2CK)
      begin
        QALE <= STATD[4] | (STATD[1] & ~(MOVX[0] & CYC[2])) | (CLEAR & ~STATD[
        5]) ; 
      end 
    end 
  end 

  always @(posedge NX2)
  begin : setpopmen
    if (!DIV2CK)
    begin
      POPMEN <= (XROM | ~NEA) & ((STATD[1] & ~CLEAR & ~(MOVX[0] & CYC[2]))
      | (STATD[4] & ~(MOVX[0] & CYC[1]))) & ~RST ; 
    end  
  end 

  always @(posedge NX2 or posedge RST)
  begin : set_port_sfrs
    if (RST)
    begin
      PORT0_SFR <= 8'b11111111 ; 
      PORT1_SFR <= 8'b11111111 ; 
      PORT2_SFR <= 8'b11111111 ; 
      PORT3_SFR <= 8'b11111111 ; 
    end
    else
    begin
      if (!DIV2CK)
      begin
        if (((EXT_PROG_EN | MOVX[0]) & AA))
        begin
          PORT0_SFR <= 8'b11111111 ; 
        end
        else if (SFRW[0])
        begin
          PORT0_SFR <= RAMDI ; 
        end 
        // set port SFRs at end of S6P2.
        // Port 0 SFR is set to ones by certain external memory operations.
        if (SFRW[1])
        begin
          PORT1_SFR <= RAMDI ; 
        end 
        if (SFRW[2])
        begin
          PORT2_SFR <= RAMDI ; 
        end 
        if (SFRW[3])
        begin
          PORT3_SFR <= RAMDI ; 
        end 
      end // not DIV2CK
    end // NX2 event
  end 

  always @(DPH or PROGRAM_ADDR or EXTDAT)
  begin : muxlocale
    case (EXTDAT)
      1'b0 :
            begin
              LOCALE <= PROGRAM_ADDR[15:8] ; 
            end
      1'b1 :
            begin
              LOCALE <= DPH ; 
            end
      default :
            begin
              LOCALE <= 8'bXXXXXXXX ; 
            end
    endcase 
  end 

  always @(posedge NX2)
  begin : setextdat
    if (CLEAR)
    begin
      EXTDAT <= 1'b0 ; 
    end
    else if (!DIV2CK)
    begin
      if ((STATD[4] & CYC[1] & MOVX[0]))
      begin
        EXTDAT <= 1'b1 ; 
      end
      else if ((STATD[4] & CYC[2]))
      begin
        EXTDAT <= 1'b0 ; 
      end 
    end  
  end