test_avr_core2.vhd

avr core porocesssor vhdl source code

library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity TEST_AVR is
end TEST_AVR;

architecture BEH of TEST_AVR is
component top_avr_core is port
(
     nrst  : in std_logic;
     clk   : in std_logic;

     porta : inout std_logic_vector(7 downto 0);
     portb : inout std_logic_vector(7 downto 0);
	 
	 -- UART 
	 rxd   : in  std_logic;
	 txd   : out std_logic
	 );
end component;

signal sg_test_porta : std_logic_vector(7 downto 0):= (others => '0');
signal sg_test_portb : std_logic_vector(7 downto 0):= (others => '0');
signal sg_test_rxd   : std_logic :='0';
signal sg_test_txd   : std_logic :='0';
signal sg_nrst       : std_logic :='0';
signal sg_clk        : std_logic :='0';
signal sg_test_ssg	 : std_logic_vector(3 downto 0):= (others => '0'); -- Seven segment decoder signal

signal cycle_counter : std_logic_vector(19 downto 0):= (others => '0');

begin

TESTING_uC:component top_avr_core port map
(
     nrst  => sg_nrst,
	 clk   => sg_clk,
     porta => sg_test_porta,
	 portb => sg_test_portb,
	 rxd   => sg_test_rxd,
	 txd   => sg_test_txd
	 );

sg_test_rxd <= sg_test_txd;	 -- Loopback
	 
-- CLOCK GENERATOR
sg_clk <= not sg_clk after 50 ns;
-- RESET 
sg_nrst <= '1' after 25 ns;

cycle_cnt:process(sg_clk,sg_nrst)
begin
if(sg_nrst='0') then
cycle_counter <= (others => '0');
elsif (sg_clk='1' and sg_clk'event) then
cycle_counter <= cycle_counter + 1;
end if;	
end process;	

-- Seven segment decoder
sg_test_ssg <= "0000" when sg_test_porta=x"3F" else -- 0
               "0001" when sg_test_porta=x"06" else	-- 1
	           "0010" when sg_test_porta=x"5B" else	-- 2
	           "0011" when sg_test_porta=x"4F" else	-- 3
	           "0100" when sg_test_porta=x"66" else	-- 4
  	           "0101" when sg_test_porta=x"6D" else	-- 5
	           "0110" when sg_test_porta=x"7D" else	-- 6
	           "0111" when sg_test_porta=x"07" else	-- 7
	           "1000" when sg_test_porta=x"7F" else	-- 8
	           "1001" when sg_test_porta=x"6F" else	-- 9
	           "1010" when sg_test_porta=x"77" else	-- A
	           "1011" when sg_test_porta=x"7C" else	-- B
	           "1100" when sg_test_porta=x"39" else	-- C
	           "1101" when sg_test_porta=x"5E" else	-- D			   
	           "1110" when sg_test_porta=x"79" else -- E
	           "1111" when sg_test_porta=x"71";   	-- F			   
				   

end beh;