timer_counter.vhd

avr core porocesssor vhdl source code

--**********************************************************************************************
--                           Timers/Counters Block Peripheral for the AVR Core
--                           Version 0.1A 15.01.2002	
--                           Designed by Ruslan Lepetenok
--**********************************************************************************************

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Timer_Counter is port(
	                   -- AVR Control
               ireset         : in std_logic;
               cp2	          : in std_logic;
               adr            : in std_logic_vector(5 downto 0);
               dbus_in        : in std_logic_vector(7 downto 0);
               dbus_out       : out std_logic_vector(7 downto 0);
               iore           : in std_logic;
               iowe           : in std_logic;
               out_en         : out std_logic; 

                       --Timer/Counters
               EXT1           : in std_logic;
               EXT2           : in std_logic;
			   Tosc1	      : in std_logic;
			   OC0_PWM0       : out std_logic;
			   OC1A_PWM1A     : out std_logic;
			   OC1B_PWM1B     : out std_logic;
			   OC2_PWM2       : out std_logic;
			   		   
			           --IRQ
               TC0OvfIRQ      : out std_logic;
			   TC0OvfIRQ_Ack  : in std_logic;
			   TC0CmpIRQ      : out std_logic;
			   TC0CmpIRQ_Ack  : in std_logic;
			   TC2OvfIRQ      : out std_logic;
			   TC2OvfIRQ_Ack  : in std_logic;
			   TC2CmpIRQ      : out std_logic;
			   TC2CmpIRQ_Ack  : in std_logic;
			   TC1OvfIRQ      : out std_logic;
			   TC1OvfIRQ_Ack  : in std_logic;
			   TC1CmpAIRQ     : out std_logic;
			   TC1CmpAIRQ_Ack : in std_logic;
			   TC1CmpBIRQ     : out std_logic;
			   TC1CmpBIRQ_Ack : in std_logic;			   
			   TC1ICIRQ       : out std_logic;
			   TC1ICIRQ_Ack   : in std_logic);
end Timer_Counter;

architecture rtl of Timer_Counter is

-- Copies of the external signals
signal OC0_PWM0_Int   :	std_logic := '0';
signal OC2_PWM2_Int   :	std_logic := '0';

-- Registers
signal TCCR0  : std_logic_vector(7 downto 0) := (others => '0');
signal TCCR1A : std_logic_vector(7 downto 0) := (others => '0');
signal TCCR1B : std_logic_vector(7 downto 0) := (others => '0');
signal TCCR2  : std_logic_vector(7 downto 0) := (others => '0');
signal ASSR   : std_logic_vector(7 downto 0) := (others => '0'); -- Asynchronous status register (for TCNT0)
signal TIMSK  : std_logic_vector(7 downto 0) := (others => '0');
signal TIFR   : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT0  : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT2  : std_logic_vector(7 downto 0) := (others => '0');
signal OCR0   : std_logic_vector(7 downto 0) := (others => '0');
signal OCR2   : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT1H : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT1L : std_logic_vector(7 downto 0) := (others => '0');
signal OCR1AH : std_logic_vector(7 downto 0) := (others => '0');
signal OCR1AL : std_logic_vector(7 downto 0) := (others => '0');
signal OCR1BH : std_logic_vector(7 downto 0) := (others => '0');
signal OCR1BL : std_logic_vector(7 downto 0) := (others => '0');
signal ICR1AH : std_logic_vector(7 downto 0) := (others => '0');
signal ICR1AL : std_logic_vector(7 downto 0) := (others => '0');

signal TCCR0_Sel  : std_logic := '0';
signal TCCR1A_Sel : std_logic := '0';
signal TCCR1B_Sel : std_logic := '0';
signal TCCR2_Sel  : std_logic := '0';
signal ASSR_Sel   : std_logic := '0';
signal TIMSK_Sel  : std_logic := '0';
signal TIFR_Sel   : std_logic := '0';
signal TCNT0_Sel  : std_logic := '0';
signal TCNT2_Sel  : std_logic := '0';
signal OCR0_Sel   : std_logic := '0';
signal OCR2_Sel   : std_logic := '0';
signal TCNT1H_Sel : std_logic := '0';
signal TCNT1L_Sel : std_logic := '0';
signal OCR1AH_Sel : std_logic := '0';
signal OCR1AL_Sel : std_logic := '0';
signal OCR1BH_Sel : std_logic := '0';
signal OCR1BL_Sel : std_logic := '0';
signal ICR1AH_Sel : std_logic := '0';
signal ICR1AL_Sel : std_logic := '0';

constant TCCR0_Address  : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#33#,adr'high+1);
constant TCCR1A_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#2F#,adr'high+1);
constant TCCR1B_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#2E#,adr'high+1);
constant TCCR2_Address  : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#25#,adr'high+1);
constant ASSR_Address   : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#30#,adr'high+1);
constant TIMSK_Address  : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#37#,adr'high+1);
constant TIFR_Address   : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#36#,adr'high+1);
constant TCNT0_Address  : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#32#,adr'high+1);
constant TCNT2_Address  : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#24#,adr'high+1);
constant OCR0_Address   : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#31#,adr'high+1);
constant OCR2_Address   : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#23#,adr'high+1);
constant TCNT1H_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#2D#,adr'high+1);
constant TCNT1L_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#2C#,adr'high+1);
constant OCR1AH_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#2B#,adr'high+1);
constant OCR1AL_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#2A#,adr'high+1);
constant OCR1BH_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#29#,adr'high+1);
constant OCR1BL_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#28#,adr'high+1);
constant ICR1AH_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#27#,adr'high+1);
constant ICR1AL_Address : std_logic_vector(adr'range) := CONV_STD_LOGIC_VECTOR(16#26#,adr'high+1);

  -- TCCR0 Bits
alias CS00  : std_logic is TCCR0(0);
alias CS01  : std_logic is TCCR0(1);
alias CS02  : std_logic is TCCR0(2);
alias CTC0  : std_logic is TCCR0(3);
alias COM00 : std_logic is TCCR0(4);
alias COM01 : std_logic is TCCR0(5);
alias PWM0  : std_logic is TCCR0(6);

  -- TCCR1A Bits
alias PWM10  : std_logic is TCCR1A(0);
alias PWM11  : std_logic is TCCR1A(1);
alias COM1B0 : std_logic is TCCR1A(4);
alias COM1B1 : std_logic is TCCR1A(5);
alias COM1A0 : std_logic is TCCR1A(4);
alias COM1A1 : std_logic is TCCR1A(5);

  -- TCCR1B Bits
alias CS10  : std_logic is TCCR1A(0);
alias CS11  : std_logic is TCCR1A(1);
alias CS12  : std_logic is TCCR1A(2);
alias CTC1  : std_logic is TCCR1A(3);
alias ICES1 : std_logic is TCCR1A(6);
alias ICNC1 : std_logic is TCCR1A(7);

  -- TCCR2 Bits
alias CS20  : std_logic is TCCR2(0);
alias CS21  : std_logic is TCCR2(1);
alias CS22  : std_logic is TCCR2(2);
alias CTC2  : std_logic is TCCR2(3);
alias COM20 : std_logic is TCCR2(4);
alias COM21 : std_logic is TCCR2(5);
alias PWM2  : std_logic is TCCR2(6);

-- ASSR bits
alias TCR0UB  : std_logic is ASSR(0);
alias OCR0UB  : std_logic is ASSR(1);
alias TCN0UB  : std_logic is ASSR(2);
alias AS0     : std_logic is ASSR(3);

-- TIMSK bits
alias TOIE0     : std_logic is TIMSK(0);
alias OCIE0     : std_logic is TIMSK(1);
alias TOIE1     : std_logic is TIMSK(2);
alias OCIE1B    : std_logic is TIMSK(3);
alias OCIE1A    : std_logic is TIMSK(4);
alias TICIE1    : std_logic is TIMSK(5);
alias TOIE2     : std_logic is TIMSK(6);
alias OCIE2     : std_logic is TIMSK(7);

-- TIFR bits
alias TOV0     : std_logic is TIFR(0);
alias OCF0     : std_logic is TIFR(1);
alias TOV1     : std_logic is TIFR(2);
alias OCF1B    : std_logic is TIFR(3);
alias OCF1A    : std_logic is TIFR(4);
alias ICF1     : std_logic is TIFR(5);
alias TOV2     : std_logic is TIFR(6);
alias OCF2     : std_logic is TIFR(7);

-- Prescaler1 signals
signal CK8    : std_logic := '0';
signal CK64   : std_logic := '0';
signal CK256  : std_logic := '0';
signal CK1024 : std_logic := '0';

signal Pre1Cnt : std_logic_vector(9 downto 0) := (others => '0'); -- Prescaler 1 counter (10-bit)

signal EXT1RE : std_logic := '0'; -- Rising edge of external input EXT1 (for TCNT1 only)
signal EXT1FE : std_logic := '0'; -- Falling edge of external input EXT1 (for TCNT1 only)

signal EXT2RE : std_logic := '0'; -- Rising edge of external input EXT2	(for TCNT2 only)
signal EXT2FE : std_logic := '0'; -- Falling edge of external input EXT2 (for TCNT2 only)

-- Risign/falling edge detectors	
signal EXT1Latched : std_logic := '0';	
signal EXT2Latched : std_logic := '0';	

-- Prescalers outputs 
signal TCNT0_En : std_logic := '0'; -- Output of the prescaler 0
signal TCNT1_En : std_logic := '0';	-- Output of the prescaler 1
signal TCNT2_En : std_logic := '0';	-- Output of the prescaler 1

-- Prescaler0 signals	
signal PCK0     : std_logic := '0';
signal PCK08    : std_logic := '0';
signal PCK032   : std_logic := '0';
signal PCK064   : std_logic := '0';
signal PCK0128  : std_logic := '0';
signal PCK0256  : std_logic := '0';
signal PCK01024 : std_logic := '0';

signal Tosc1RE      : std_logic := '0'; -- Rising edge detector for TOSC1 input
signal Tosc1Latched : std_logic := '0';
signal Pre0Cnt      : std_logic_vector(9 downto 0) := (others => '0'); -- Prescaler 0 counter (10-bit)

signal PCK0_Del     : std_logic := '0';

-- Timer/counter 0 signals
signal TCNT0_Tmp     : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT0_In      : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT0_Imm_In  : std_logic_vector(7 downto 0) := (others => '0'); -- Immediate data input 
signal TCCR0_Tmp     : std_logic_vector(7 downto 0) := (others => '0');
signal TCCR0_In      : std_logic_vector(7 downto 0) := (others => '0');
signal OCR0_Tmp      : std_logic_vector(7 downto 0) := (others => '0');
signal OCR0_In       : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT0_Cnt_Dir : std_logic := '0'; -- Count up(0) down (1)
signal TCNT0_Clr     : std_logic := '0'; -- Clear (syncronously) TCNT0
signal TCNT0_Ld_Imm  : std_logic := '0'; -- Load immediate value (syncronously) TCNT0
signal TCNT0_Cmp_Out : std_logic := '0'; -- Output of the comparator
signal TCNT0_Inc     : std_logic := '0'; -- Increment (not load) took place

-- For asynchronous mode only
signal TCR0UB_Tmp     : std_logic := '0';
signal OCR0UB_Tmp     : std_logic := '0';
signal TCN0UB_Tmp     : std_logic := '0';

-- Timer/counter 2 signals
signal TCNT2_In      : std_logic_vector(7 downto 0) := (others => '0');
signal OCR2_Tmp      : std_logic_vector(7 downto 0) := (others => '0');
signal TCNT2_Cnt_Dir : std_logic := '0'; -- Count up(0) down (1)
signal TCNT2_Clr     : std_logic := '0'; -- Clear (syncronously) TCNT0
-- TBD

-- Timer/counter 1 signals
-- TBD

-- Additonal signals (These signals are added in order to emulate the behaviour of the real chip )
-- !!! TBD !!!
--signal PORTB4_Out : std_logic := '0';
--signal PORTB5_Out : std_logic := '0';
--signal PORTB6_Out : std_logic := '0';
--signal PORTB7_Out : std_logic := '0';

begin
	
-- Prescaler 1 for TCNT1 and TCNT2
Prescaler_1:process(cp2,ireset)
begin
if (ireset='0') then                 -- Reset
 Pre1Cnt <= (others => '0'); 
 CK8 <= '0';
 CK64 <= '0';
 CK256 <= '0';
 CK1024 <= '0';
 EXT1RE <= '0';
 EXT1FE <= '0';
 EXT2RE <= '0';
 EXT2FE <= '0';
 EXT1Latched <= '0';
 EXT2Latched <= '0';
  elsif (cp2='1' and cp2'event) then -- Clock
    Pre1Cnt <= Pre1Cnt+1;
	 CK8 <= not CK8 and(Pre1Cnt(0) and Pre1Cnt(1)and Pre1Cnt(2));
     CK64 <= not CK64 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5));
     CK256 <= not CK256 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7));
     CK1024 <= not CK1024 and(Pre1Cnt(0) and Pre1Cnt(1) and Pre1Cnt(2) and Pre1Cnt(3) and Pre1Cnt(4) and Pre1Cnt(5) and Pre1Cnt(6) and Pre1Cnt(7) and Pre1Cnt(8) and Pre1Cnt(9));
     EXT1RE <= not EXT1RE and (EXT1 and not EXT1Latched);
     EXT1FE <= not EXT1FE and (not EXT1 and EXT1Latched);
     EXT2RE <= not EXT2RE and (EXT2 and not EXT2Latched);
     EXT2FE <= not EXT2FE and (not EXT2 and EXT2Latched);
     EXT1Latched <= Ext1;
     EXT2Latched <= Ext2;  
  end if;
end process;		

TCNT1_En <= (not CS12 and not CS11 and CS10) or            -- CK             "001"
            (CK8 and not CS12 and CS11 and not CS10) or    -- CK/8			 "010"
			(CK64 and not CS12 and CS11 and CS10)    or    -- CK/64			 "011"
			(CK256 and CS12 and not CS11 and not CS10) or  -- CK/256		 "100"
            (CK64 and CS12 and not CS11 and CS10)    or    -- CK/1024		 "101"
			(EXT1FE and CS12 and CS11 and not CS10) or     -- Falling edge	 "110"
            (EXT1RE and CS12 and CS11 and CS10);           -- Rising edge	 "111"
			
TCNT2_En <= (not CS22 and not CS21 and CS20) or            -- CK             "001"
            (CK8 and not CS22 and CS21 and not CS20) or    -- CK/8			 "010"
			(CK64 and not CS22 and CS21 and CS20)    or    -- CK/64			 "011"
			(CK256 and CS22 and not CS21 and not CS20) or  -- CK/256		 "100"
            (CK64 and CS22 and not CS21 and CS20)    or    -- CK/1024		 "101"
			(EXT2FE and CS22 and CS21 and not CS20) or     -- Falling edge	 "110"
            (EXT2RE and CS22 and CS21 and CS20);           -- Rising edge	 "111"


-- Prescaler 0 for TCNT0
Tosc1_Rising_Edge_Detector:process(cp2,ireset)
begin
 if ireset='0' then  --Reset
  Tosc1RE <= '0';