📄 pm_fetch_dec.vhd
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--************************************************************************************************
-- PM_FETCH_DEC(internal module) for AVR core
-- Version 2.1
-- Designed by Ruslan Lepetenok 14.11.2001
-- Modified 20.01.2002
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity pm_fetch_dec is port
(
-- EXTERNAL INTERFACES OF THE CORE
clk : in std_logic;
nrst : in std_logic;
cpuwait : in std_logic;
-- PROGRAM MEMORY PORTS
pc : out std_logic_vector (15 downto 0); -- CORE OUTPUT !CHECKED!
inst : in std_logic_vector (15 downto 0); -- CORE INPUT !CHECKED!
-- I/O REGISTERS PORTS
adr : out std_logic_vector (5 downto 0); -- CORE OUTPUT ????
iore : out std_logic; -- CORE OUTPUT !CHECKED!
iowe : out std_logic; -- CORE OUTPUT !CHECKED!
-- DATA MEMORY PORTS
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- INTERRUPTS PORT
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
-- END OF THE CORE INTERFACES
-- *********************************************************************************************
-- ******************** INTERFACES TO THE OTHER BLOCKS *****************************************
-- *********************************************************************************************
-- *********************************************************************************************
-- ******************** INTERFACES TO THE ALU *************************************************
-- *********************************************************************************************
alu_data_r_in : out std_logic_vector(7 downto 0);
alu_data_d_in : out std_logic_vector(7 downto 0);
-- OPERATION SIGNALS INPUTS
idc_add_out : out std_logic;
idc_adc_out : out std_logic;
idc_adiw_out : out std_logic;
idc_sub_out : out std_logic;
idc_subi_out : out std_logic;
idc_sbc_out : out std_logic;
idc_sbci_out : out std_logic;
idc_sbiw_out : out std_logic;
adiw_st_out : out std_logic;
sbiw_st_out : out std_logic;
idc_and_out : out std_logic;
idc_andi_out : out std_logic;
idc_or_out : out std_logic;
idc_ori_out : out std_logic;
idc_eor_out : out std_logic;
idc_com_out : out std_logic;
idc_neg_out : out std_logic;
idc_inc_out : out std_logic;
idc_dec_out : out std_logic;
idc_cp_out : out std_logic;
idc_cpc_out : out std_logic;
idc_cpi_out : out std_logic;
idc_cpse_out : out std_logic;
idc_lsr_out : out std_logic;
idc_ror_out : out std_logic;
idc_asr_out : out std_logic;
idc_swap_out : out std_logic;
-- DATA OUTPUT
alu_data_out : in std_logic_vector(7 downto 0);
-- FLAGS OUTPUT
alu_c_flag_out : in std_logic;
alu_z_flag_out : in std_logic;
alu_n_flag_out : in std_logic;
alu_v_flag_out : in std_logic;
alu_s_flag_out : in std_logic;
alu_h_flag_out : in std_logic;
-- *********************************************************************************************
-- ******************** INTERFACES TO THE GENERAL PURPOSE REGISTER FILE ************************
-- *********************************************************************************************
reg_rd_in : out std_logic_vector (7 downto 0);
reg_rd_out : in std_logic_vector (7 downto 0);
reg_rd_adr : out std_logic_vector (4 downto 0);
reg_rr_out : in std_logic_vector (7 downto 0);
reg_rr_adr : out std_logic_vector (4 downto 0);
reg_rd_wr : out std_logic;
post_inc : out std_logic; -- POST INCREMENT FOR LD/ST INSTRUCTIONS
pre_dec : out std_logic; -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
reg_h_wr : out std_logic;
reg_h_out : in std_logic_vector (15 downto 0);
reg_h_adr : out std_logic_vector (2 downto 0); -- x,y,z
reg_z_out : in std_logic_vector (15 downto 0); -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
-- *********************************************************************************************
-- ******************** INTERFACES TO THE INPUT/OUTPUT REGISTER FILE ***************************
-- *********************************************************************************************
-- adr : out std_logic_vector(5 downto 0);
-- iowe : out std_logic;
-- dbusout : out std_logic_vector(7 downto 0); -- OUTPUT OF THE CORE
sreg_fl_in : out std_logic_vector(7 downto 0); -- ????
sreg_out : in std_logic_vector(7 downto 0); -- ????
sreg_fl_wr_en : out std_logic_vector(7 downto 0); --FLAGS WRITE ENABLE SIGNALS
spl_out : in std_logic_vector(7 downto 0);
sph_out : in std_logic_vector(7 downto 0);
sp_ndown_up : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
sp_en : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
rampz_out : in std_logic_vector(7 downto 0);
-- *********************************************************************************************
-- ******************** INTERFACES TO THE INPUT/OUTPUT ADDRESS DECODER ************************
-- *********************************************************************************************
-- ram_data_in : in std_logic_vector (7 downto 0);
-- adr : in std_logic_vector(5 downto 0);
-- iore : in std_logic; -- CORE SIGNAL
-- ramre : in std_logic; -- CORE SIGNAL
-- dbusin : out std_logic_vector(7 downto 0)); -- CORE SIGNAL
-- *********************************************************************************************
-- ******************** INTERFACES TO THE BIT PROCESSOR **************************************
-- *********************************************************************************************
bit_num_r_io : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
-- dbusin : in std_logic_vector(7 downto 0); -- SBI/CBI/SBIS/SBIC IN
bitpr_io_out : in std_logic_vector(7 downto 0); -- SBI/CBI OUT
brunch_cond : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRUNCH CONDITION FOR BRBS/BRBC INSTRUCTION
bit_pr_sreg_out : in std_logic_vector(7 downto 0); -- BCLR/BSET/BST(T-FLAG ONLY)
sreg_bit_num : out std_logic_vector(2 downto 0); -- BIT NUMBER FOR BCLR/BSET INSTRUCTIONS
bld_op_out : in std_logic_vector(7 downto 0); -- BLD OUT (T FLAG)
bit_test_op_out : in std_logic; -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
-- OPERATION SIGNALS INPUTS
-- INSTRUCTUIONS AND STATES
idc_sbi_out : out std_logic;
sbi_st_out : out std_logic;
idc_cbi_out : out std_logic;
cbi_st_out : out std_logic;
idc_bld_out : out std_logic;
idc_bst_out : out std_logic;
idc_bset_out : out std_logic;
idc_bclr_out : out std_logic;
idc_sbic_out : out std_logic;
idc_sbis_out : out std_logic;
idc_sbrs_out : out std_logic;
idc_sbrc_out : out std_logic;
idc_brbs_out : out std_logic;
idc_brbc_out : out std_logic;
idc_reti_out : out std_logic
-- *********************************************************************************************
-- ******************** END OF INTERFACES TO THE OTHER BLOCKS *********************************
-- *********************************************************************************************
);
end pm_fetch_dec;
architecture rtl of pm_fetch_dec is
-- COPIES OF OUTPUTS
signal ramadr_reg_in : std_logic_vector(15 downto 0) :=(others =>'0'); -- INPUT OF THE ADDRESS REGISTER
signal ramadr_reg_en : std_logic; -- ADRESS REGISTER CLOCK ENABLE SIGNAL
signal irqack_int : std_logic;
signal irqackad_int : std_logic_vector(irqackad'range) :=(others =>'0');
-- ####################################################
-- INTERNAL SIGNALS
-- ####################################################
-- NEW SIGNALS
signal two_word_inst : std_logic; -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
signal ram_adr_int : std_logic_vector (15 downto 0):=(others =>'0');
constant const_ram_to_reg : std_logic_vector := "00000000000"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
constant const_ram_to_io_a : std_logic_vector := "00000000001"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
constant const_ram_to_io_b : std_logic_vector := "00000000010"; -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
-- LD/LDD/ST/STD SIGNALS
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0):=(others =>'0');
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0):=(others =>'0');
-- PROGRAM COUNTER SIGNALS
signal program_counter_tmp : std_logic_vector (15 downto 0):=(others =>'0'); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
signal program_counter : std_logic_vector (15 downto 0):=(others =>'0');
signal program_counter_in : std_logic_vector (15 downto 0):=(others =>'0');
signal program_counter_high_fr : std_logic_vector (7 downto 0):=(others =>'0'); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
signal pc_low : std_logic_vector (7 downto 0):=(others =>'0');
signal pc_high : std_logic_vector (7 downto 0):=(others =>'0');
signal pc_low_en : std_logic;
signal pc_high_en : std_logic;
signal offset_brbx : std_logic_vector (15 downto 0):=(others =>'0'); -- OFFSET FOR BRCS/BRCC INSTRUCTION !!CHECKED
signal offset_rxx : std_logic_vector (15 downto 0):=(others =>'0'); -- OFFSET FOR RJMP/RCALL INSTRUCTION !!CHECKED
signal pa15_pm : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
signal alu_reg_wr : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS AND INTERRUPT
signal reg_file_adr_space : std_logic; -- ACCSESS TO THE REGISTER FILE
signal io_file_adr_space : std_logic; -- ACCSESS TO THE I/O FILE
-- STATE MACHINES SIGNALS
signal irq_start : std_logic := '0';
signal nirq_st0 : std_logic := '0';
signal irq_st1 : std_logic := '0';
signal irq_st2 : std_logic := '0';
signal irq_st3 : std_logic := '0';
signal ncall_st0 : std_logic := '0';
signal call_st1 : std_logic := '0';
signal call_st2 : std_logic := '0';
signal call_st3 : std_logic := '0';
signal nrcall_st0 : std_logic := '0';
signal rcall_st1 : std_logic := '0';
signal rcall_st2 : std_logic := '0';
signal nicall_st0 : std_logic := '0';
signal icall_st1 : std_logic := '0';
signal icall_st2 : std_logic := '0';
signal njmp_st0 : std_logic := '0';
signal jmp_st1 : std_logic := '0';
signal jmp_st2 : std_logic := '0';
signal ijmp_st : std_logic := '0';
signal rjmp_st : std_logic := '0';
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