cpuwait.vhd

avr core porocesssor vhdl source code

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity cpuwait is port (
          clk       : in std_logic;
          nrst      : in std_logic;
	  		  
	      cpuwait  : out std_logic;		  
	      ramwe	   : in  std_logic;
		  ramre	   : in  std_logic
		               );

end cpuwait;

architecture beh of cpuwait is
begin

cpuwait   <= '0';

end beh;