ram.vhd

avr core porocesssor vhdl source code

--************************************************************************************************
-- Data RAM for AVR core
-- Version 2.0
-- Designed by Ruslan Lepetenok 13.11.2001
--************************************************************************************************

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity ram is 
		  generic(ram_size :positive := 128; address_width : positive := 7);
	      port (
          cp2         : in std_logic;
  	      address     : in  std_logic_vector (address_width-1 downto 0);
		  ramwe		  : in  std_logic;
		  din         : in  std_logic_vector (7 downto 0);
		  dout        : out	std_logic_vector (7 downto 0));

end ram;

architecture rtl of ram is
type ram_file_type is array (0 to ram_size-1) of std_logic_vector (7 downto 0);
signal ram_file : ram_file_type := (others =>"00000000");
signal ram_file_out_mux : ram_file_type := (others =>"00000000");  

begin
	
RAM_WRITE:process(cp2)
begin
if (cp2='1' and cp2'event) then
for i in 0 to ram_size-1 loop
if (i=address and ramwe='1') then
ram_file(i) <= din;
end if;
end loop;
end if;
end process;

ram_file_out_mux(0) <= ram_file(0) when address=0 else (others => '0');
out_mux: for i in 1 to ram_size-1 generate	
ram_file_out_mux(i) <= ram_file(i) when i=address else ram_file_out_mux(i-1);
end generate;	
dout <= ram_file_out_mux(ram_size-1);

end rtl;