io_adr_dec.vhd

avr core porocesssor vhdl source code

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity io_adr_dec is port (
          adr          : in std_logic_vector(5 downto 0);         
          iore         : in std_logic;         
          dbusin_ext   : in std_logic_vector(7 downto 0);
          dbusin_int   : out std_logic_vector(7 downto 0);
                    
          spl_out      : in std_logic_vector(7 downto 0); 
          sph_out      : in std_logic_vector(7 downto 0);           
          sreg_out     : in std_logic_vector(7 downto 0);           
          rampz_out    : in std_logic_vector(7 downto 0));
end io_adr_dec;

architecture rtl of io_adr_dec is
constant sreg_io_adr  : std_logic_vector (5 downto 0):= "111111";
constant sph_io_adr   : std_logic_vector (5 downto 0):= "111110";
constant spl_io_adr   : std_logic_vector (5 downto 0):= "111101";
constant rampz_io_adr : std_logic_vector (5 downto 0):= "111011";


begin

dbusin_int <= spl_out   when (adr=spl_io_adr  and iore='1') else
              sph_out  when  (adr=sph_io_adr  and iore='1') else
              sreg_out when  (adr=sreg_io_adr  and iore='1') else
              rampz_out when (adr=rampz_io_adr and iore='1') else
              dbusin_ext;

end rtl;