top_avr_core.vhd

avr core porocesssor vhdl source code

signal sg_portb_out_en : std_logic := '0';

-- UART
signal sg_uart_dbusout : std_logic_vector (7 downto 0) := (others => '0');
signal sg_uart_out_en  : std_logic := '0';

signal sg_uart_tx_en  : std_logic := '0';
signal sg_uart_rx_en  : std_logic := '0';

-- Timer/Counter
signal sg_tc_dbusout : std_logic_vector (7 downto 0) := (others => '0');
signal sg_tc_out_en  : std_logic := '0';

-- Service module
signal sg_sm_dbusout : std_logic_vector (7 downto 0) := (others => '0');
signal sg_sm_out_en  : std_logic := '0';

-- ###############################################################################################################


-- ####################### Signals connected directly to the external multiplexer ################################
signal   sg_io_port_out     : ext_mux_din_type := (others => "00000000");
signal   sg_io_port_out_en  : ext_mux_en_type      := (others => '0');
signal   sg_ind_irq_ack     : std_logic_vector(sg_core_irqlines'range) := (others => '0');
-- ###############################################################################################################


-- ********************************** External interrupts signals ********************
signal sg_ext_int_req : std_logic_vector(7 downto 0) := (others => '0');

-- ***********************************************************************************

begin

TESTING_CORE: component avr_core  port map
(

cp2      => clk,    
ireset   => nrst,
cpuwait  => sg_core_cpuwait,

-- PROGRAM MEMORY PORTS
pc       => sg_core_pc,
inst     => sg_core_inst,

-- I/O REGISTERS PORTS
adr      => sg_core_adr,
iore     => sg_core_iore,
iowe     => sg_core_iowe,

-- DATA MEMORY PORTS
ramadr  => sg_core_ramadr,
ramre   => sg_core_ramre,
ramwe   => sg_core_ramwe,

dbusin   => sg_core_dbusin,
dbusout  => sg_core_dbusout,

-- INTERRUPTS PORT
irqlines => sg_core_irqlines, 
irqack   => sg_core_irqack,
irqackad => sg_core_irqackad 

);


pr:component prom port map
(
address_in  => sg_core_pc,
data_out    => sg_core_inst
);


RAM_DATA_TRIGGER:process(clk,nrst)
begin
if (nrst='0') then                        -- RESET
 sg_ram_din <= (others => '0');
  elsif(clk='1' and clk'event) then       -- CLOCK
   if (sg_core_cpuwait='0') then          -- CLOCK ENABLE
    sg_ram_din <=sg_core_dbusout;
   end if;	
end if;	
end process;

sg_ram_din_comb <= sg_ram_din;

DATA_RAM: component ram 
		  generic map(ram_size => 128,address_width => 7)
	      port map (
          cp2      => clk,     
  	  	  address  => sg_core_ramadr(6 downto 0),
		  ramwe	   => sg_core_ramwe,
		  din      => sg_ram_din_comb,
		  dout     => sg_ram_dout);

EXT_MUX:component external_mux port map(
		  ramre              => sg_core_ramre,		  -- ramre output of the core
		  dbus_out           => sg_core_dbusin,       -- Data input of the core 
		  ram_data_out       => sg_ram_dout,          -- Data output of the RAM
		  io_port_bus        => sg_io_port_out,       -- Data outputs of the I/O
		  io_port_en_bus     => sg_io_port_out_en,    -- Out enable outputs of I/O
		  irqack             => sg_core_irqack,		  
		  irqackad			 => sg_core_irqackad,
		  ind_irq_ack		 =>	sg_ind_irq_ack		  -- Individual interrupt acknolege for the peripheral
                                            );


-- ******************  PORTA **************************				
PORTA_COMP:component pport  
	generic map(PORTX_Adr => 16#1B# ,DDRX_Adr => 16#1A#, PINX_Adr => 16#19#)
	port map(
	                   -- AVR Control
               ireset     => nrst,
               cp2	      => clk, 
               adr        => sg_core_adr,
               dbus_in    => sg_core_dbusout,
               dbus_out   => sg_porta_dbusout,
               iore       => sg_core_iore,
               iowe       => sg_core_iowe,
               out_en     => sg_porta_out_en,
			            -- External connection
			   pinx       => porta);

-- PORTA connection to the external multiplexer
sg_io_port_out(0) <= sg_porta_dbusout;
sg_io_port_out_en(0) <= sg_porta_out_en;

-- ******************  PORTB **************************		
PORTB_COMP:component pport 
	generic map (PORTX_Adr =>16#18# ,DDRX_Adr => 16#17#, PINX_Adr => 16#16#)
	port map(
	                   -- AVR Control
               ireset     => nrst,
               cp2	      => clk, 
               adr        => sg_core_adr,
               dbus_in    => sg_core_dbusout,
               dbus_out   => sg_portb_dbusout,
               iore       => sg_core_iore,
               iowe       => sg_core_iowe,
               out_en     => sg_portb_out_en,
			            -- External connection
			   pinx       => portb);

-- PORTB connection to the external multiplexer
sg_io_port_out(1) <= sg_portb_dbusout;
sg_io_port_out_en(1) <= sg_portb_out_en;

-- ************************************************
TEST_CPUWAIT: component cpuwait port map (
          clk       => clk,
          nrst      => nrst,
		  		  
		  cpuwait  	=> sg_core_cpuwait,
	      ramwe	   	=> sg_core_ramwe,
		  ramre	    => sg_core_ramre);

-- Simple timer		  
TIMER:component simple_timer port map(
ireset       => nrst,
cp2          => clk,
irqline      => sg_ext_int_req(0),    
timer_irqack => sg_ind_irq_ack(0)
                                     );

sg_core_irqlines(22 downto 20) <= (others => '0');
sg_core_irqlines(13 downto 8)  <= (others => '0');
-- ************************


UART_AVR:component uart port map(
	                   -- AVR Control
               ireset     => nrst,
               cp2	      => clk,
               adr        => sg_core_adr,
               dbus_in    => sg_core_dbusout,
               dbus_out   => sg_uart_dbusout, 
               iore       => sg_core_iore,
               iowe       => sg_core_iowe,
               out_en     => sg_uart_out_en,

                       --UART
               rxd        => rxd,
               rx_en      => sg_uart_rx_en,
               txd        => txd,
               tx_en      => sg_uart_tx_en,

                       --IRQ
               txcirq     => sg_core_irqlines(19),    -- UART TX Comleet Handler ($0028)
               txc_irqack => sg_ind_irq_ack(19),
               udreirq    => sg_core_irqlines(18),	-- UART Empty ($0026)
			   rxcirq     => sg_core_irqlines(17)   -- UART RX Comleet Handler ($0024)
                              );

-- UART connection to the external multiplexer							  
sg_io_port_out(2)    <= sg_uart_dbusout;
sg_io_port_out_en(2) <= sg_uart_out_en;

-- Timer/Counter
TIM_CNT:component Timer_Counter port map(
	                   -- AVR Control
               ireset     => nrst,
               cp2	      => clk,
               adr        => sg_core_adr,
               dbus_in    => sg_core_dbusout,
               dbus_out   => sg_tc_dbusout, 
               iore       => sg_core_iore,
               iowe       => sg_core_iowe,
               out_en     => sg_tc_out_en,

                       --Timer/Counters
               EXT1           => '0',
               EXT2           => '0',
			   Tosc1	      => '0',
--			   OC0_PWM0       => ,
--			   OC1A_PWM1A     => ,
--			   OC1B_PWM1B     => ,
--			   OC2_PWM2       => ,
			   		   
			           --IRQ
               TC0OvfIRQ      => sg_core_irqlines(15),  -- Timer/Counter0 overflow ($0020)
			   TC0OvfIRQ_Ack  => sg_ind_irq_ack(15),
			   TC0CmpIRQ      => sg_core_irqlines(14),  -- Timer/Counter0 Compare Match ($001E)
			   TC0CmpIRQ_Ack  => sg_ind_irq_ack(15),
--			   TC2OvfIRQ      => ,
			   TC2OvfIRQ_Ack  => '0',
--			   TC2CmpIRQ      => ,
			   TC2CmpIRQ_Ack  => '0',
--			   TC1OvfIRQ      => ,
			   TC1OvfIRQ_Ack  => '0',
--			   TC1CmpAIRQ     => ,
			   TC1CmpAIRQ_Ack => '0',
--			   TC1CmpBIRQ     => ,
			   TC1CmpBIRQ_Ack => '0',
--			   TC1ICIRQ       => ,
			   TC1ICIRQ_Ack   => '0');

-- Timer/Counter connection to the external multiplexer							  
sg_io_port_out(3)    <= sg_tc_dbusout;
sg_io_port_out_en(3) <= sg_tc_out_en;


Serv_Module:component Service_Module port map(
	                   -- AVR Control
               ireset         => nrst,
               cp2	          => clk,
               adr            => sg_core_adr,
               dbus_in        => sg_core_dbusout,
               dbus_out       => sg_sm_dbusout, 
               iore           => sg_core_iore,
               iowe           => sg_core_iowe,
               out_en         => sg_sm_out_en,
			        -- SLEEP mode signals
--			   sleep_en       : out std_logic;
		   	        -- SRAM control signals
--			   ESRAM_en       : out std_logic;
--			   ESRAM_WS       : out std_logic;
			   	    --IRQ
               ExtInt_IRQ     => sg_core_irqlines(7 downto 0),
			   ExtInt_IRQ_Ack => sg_ind_irq_ack(7 downto 4),
			   
			   -- External interrupts (inputs)
			   Ext_Int_In     => sg_ext_int_req);

-- Service module connection to the external multiplexer							  
sg_io_port_out(4)    <= sg_sm_dbusout;
sg_io_port_out_en(4) <= sg_sm_out_en;                  
			   
end struct;