vga_dis.tan.rpt

cpld实现vga驱动的程序

; N/A   ; None         ; 17.978 ns  ; x_cnt[7]  ; vga_r ; clk        ;
; N/A   ; None         ; 17.868 ns  ; x_cnt[5]  ; vga_r ; clk        ;
; N/A   ; None         ; 17.840 ns  ; x_cnt[8]  ; vga_g ; clk        ;
; N/A   ; None         ; 17.583 ns  ; y_cnt[7]  ; vga_r ; clk        ;
; N/A   ; None         ; 17.344 ns  ; x_cnt[6]  ; vga_r ; clk        ;
; N/A   ; None         ; 17.085 ns  ; x_cnt[8]  ; vga_r ; clk        ;
; N/A   ; None         ; 17.046 ns  ; y_cnt[9]  ; vga_r ; clk        ;
; N/A   ; None         ; 17.043 ns  ; x_cnt[9]  ; vga_r ; clk        ;
; N/A   ; None         ; 15.953 ns  ; x_cnt[10] ; vga_b ; clk        ;
; N/A   ; None         ; 15.940 ns  ; x_cnt[10] ; vga_g ; clk        ;
; N/A   ; None         ; 14.809 ns  ; x_cnt[10] ; vga_r ; clk        ;
; N/A   ; None         ; 8.887 ns   ; hsync_r   ; hsync ; clk        ;
; N/A   ; None         ; 8.493 ns   ; vsync_r   ; vsync ; clk        ;
+-------+--------------+------------+-----------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jan 02 22:37:23 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_dis -c vga_dis
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 109.25 MHz between source register "x_cnt[10]" and destination register "y_cnt[9]" (period= 9.153 ns)
    Info: + Longest register to register delay is 8.444 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'x_cnt[10]'
        Info: 2: + IC(1.328 ns) + CELL(0.740 ns) = 2.068 ns; Loc. = LC_X5_Y4_N6; Fanout = 1; COMB Node = 'Equal0~66'
        Info: 3: + IC(0.716 ns) + CELL(0.914 ns) = 3.698 ns; Loc. = LC_X5_Y4_N1; Fanout = 5; COMB Node = 'Equal0~67'
        Info: 4: + IC(2.002 ns) + CELL(0.747 ns) = 6.447 ns; Loc. = LC_X5_Y2_N0; Fanout = 2; COMB Node = 'y_cnt[0]~165'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 6.570 ns; Loc. = LC_X5_Y2_N1; Fanout = 2; COMB Node = 'y_cnt[1]~166'
        Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 6.693 ns; Loc. = LC_X5_Y2_N2; Fanout = 2; COMB Node = 'y_cnt[2]~167'
        Info: 7: + IC(0.000 ns) + CELL(0.123 ns) = 6.816 ns; Loc. = LC_X5_Y2_N3; Fanout = 2; COMB Node = 'y_cnt[3]~168'
        Info: 8: + IC(0.000 ns) + CELL(0.261 ns) = 7.077 ns; Loc. = LC_X5_Y2_N4; Fanout = 5; COMB Node = 'y_cnt[4]~169'
        Info: 9: + IC(0.000 ns) + CELL(1.367 ns) = 8.444 ns; Loc. = LC_X5_Y2_N9; Fanout = 5; REG Node = 'y_cnt[9]'
        Info: Total cell delay = 4.398 ns ( 52.08 % )
        Info: Total interconnect delay = 4.046 ns ( 47.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 23; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N9; Fanout = 5; REG Node = 'y_cnt[9]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 23; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'x_cnt[10]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "vga_b" through register "y_cnt[0]" is 20.879 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 23; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N0; Fanout = 9; REG Node = 'y_cnt[0]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 17.155 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N0; Fanout = 9; REG Node = 'y_cnt[0]'
        Info: 2: + IC(1.298 ns) + CELL(0.978 ns) = 2.276 ns; Loc. = LC_X6_Y2_N0; Fanout = 2; COMB Node = 'Add3~256'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.399 ns; Loc. = LC_X6_Y2_N1; Fanout = 2; COMB Node = 'Add3~258'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.522 ns; Loc. = LC_X6_Y2_N2; Fanout = 2; COMB Node = 'Add3~246'
        Info: 5: + IC(0.000 ns) + CELL(0.815 ns) = 3.337 ns; Loc. = LC_X6_Y2_N3; Fanout = 5; COMB Node = 'Add3~247'
        Info: 6: + IC(2.073 ns) + CELL(0.740 ns) = 6.150 ns; Loc. = LC_X5_Y3_N7; Fanout = 1; COMB Node = 'LessThan14~125'
        Info: 7: + IC(0.711 ns) + CELL(0.740 ns) = 7.601 ns; Loc. = LC_X5_Y3_N4; Fanout = 2; COMB Node = 'LessThan14~126'
        Info: 8: + IC(0.757 ns) + CELL(0.511 ns) = 8.869 ns; Loc. = LC_X5_Y3_N1; Fanout = 2; COMB Node = 'vga_g~595'
        Info: 9: + IC(0.717 ns) + CELL(0.740 ns) = 10.326 ns; Loc. = LC_X5_Y3_N0; Fanout = 1; COMB Node = 'vga_g~600'
        Info: 10: + IC(1.191 ns) + CELL(0.511 ns) = 12.028 ns; Loc. = LC_X4_Y3_N2; Fanout = 2; COMB Node = 'vga_b~26'
        Info: 11: + IC(0.725 ns) + CELL(0.200 ns) = 12.953 ns; Loc. = LC_X4_Y3_N6; Fanout = 1; COMB Node = 'vga_b~27'
        Info: 12: + IC(1.880 ns) + CELL(2.322 ns) = 17.155 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'vga_b'
        Info: Total cell delay = 7.803 ns ( 45.49 % )
        Info: Total interconnect delay = 9.352 ns ( 54.51 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Fri Jan 02 22:37:24 2009
    Info: Elapsed time: 00:00:01