vga_dis.fit.qmsg

cpld实现vga驱动的程序

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "17.014 ns register pin " "Info: Estimated most critical path is register to pin delay of 17.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x_cnt\[0\] 1 REG LAB_X5_Y4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y4; Fanout = 9; REG Node = 'x_cnt\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { x_cnt[0] } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.348 ns) + CELL(0.978 ns) 2.326 ns Add2~300 2 COMB LAB_X4_Y4 2 " "Info: 2: + IC(1.348 ns) + CELL(0.978 ns) = 2.326 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~300'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.326 ns" { x_cnt[0] Add2~300 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.449 ns Add2~302 3 COMB LAB_X4_Y4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.449 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~302'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~300 Add2~302 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.572 ns Add2~298 4 COMB LAB_X4_Y4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.572 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~298'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~302 Add2~298 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.695 ns Add2~293 5 COMB LAB_X4_Y4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.695 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~293'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { Add2~298 Add2~293 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 3.094 ns Add2~295 6 COMB LAB_X4_Y4 5 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 3.094 ns; Loc. = LAB_X4_Y4; Fanout = 5; COMB Node = 'Add2~295'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.399 ns" { Add2~293 Add2~295 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 4.328 ns Add2~307 7 COMB LAB_X4_Y4 4 " "Info: 7: + IC(0.000 ns) + CELL(1.234 ns) = 4.328 ns; Loc. = LAB_X4_Y4; Fanout = 4; COMB Node = 'Add2~307'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { Add2~295 Add2~307 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.914 ns) 6.602 ns d_dis~352 8 COMB LAB_X3_Y3 1 " "Info: 8: + IC(1.360 ns) + CELL(0.914 ns) = 6.602 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'd_dis~352'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { Add2~307 d_dis~352 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.069 ns) + CELL(0.511 ns) 8.182 ns c_dis~128 9 COMB LAB_X4_Y3 1 " "Info: 9: + IC(1.069 ns) + CELL(0.511 ns) = 8.182 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'c_dis~128'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.580 ns" { d_dis~352 c_dis~128 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 9.362 ns c_dis~129 10 COMB LAB_X4_Y3 1 " "Info: 10: + IC(0.440 ns) + CELL(0.740 ns) = 9.362 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'c_dis~129'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { c_dis~128 c_dis~129 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 10.542 ns vga_b~25 11 COMB LAB_X4_Y3 1 " "Info: 11: + IC(0.980 ns) + CELL(0.200 ns) = 10.542 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'vga_b~25'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { c_dis~129 vga_b~25 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 11.722 ns vga_b~26 12 COMB LAB_X4_Y3 2 " "Info: 12: + IC(0.266 ns) + CELL(0.914 ns) = 11.722 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'vga_b~26'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { vga_b~25 vga_b~26 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 12.902 ns vga_g~602 13 COMB LAB_X4_Y3 1 " "Info: 13: + IC(0.266 ns) + CELL(0.914 ns) = 12.902 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'vga_g~602'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { vga_b~26 vga_g~602 } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.790 ns) + CELL(2.322 ns) 17.014 ns vga_g 14 PIN PIN_35 0 " "Info: 14: + IC(1.790 ns) + CELL(2.322 ns) = 17.014 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'vga_g'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.112 ns" { vga_g~602 vga_g } "NODE_NAME" } } { "vga_dis.v" "" { Text "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.495 ns ( 55.81 % ) " "Info: Total cell delay = 9.495 ns ( 55.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.519 ns ( 44.19 % ) " "Info: Total interconnect delay = 7.519 ns ( 44.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "17.014 ns" { x_cnt[0] Add2~300 Add2~302 Add2~298 Add2~293 Add2~295 Add2~307 d_dis~352 c_dis~128 c_dis~129 vga_b~25 vga_b~26 vga_g~602 vga_g } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "8 8 " "Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "157 " "Info: Allocated 157 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 02 22:37:14 2009 " "Info: Processing ended: Fri Jan 02 22:37:14 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.fit.smsg " "Info: Generated suppressed messages file E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}