vga_dis.fit.rpt

cpld实现vga驱动的程序

; 19                                           ; 0                            ;
; 20                                           ; 2                            ;
+----------------------------------------------+------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff          ;
; Mid Wire Use - Fit Attempt 1                                                   ; 27          ;
; Mid Slack - Fit Attempt 1                                                      ; -23311      ;
; Internal Atom Count - Fit Attempt 1                                            ; 106         ;
; LE/ALM Count - Fit Attempt 1                                                   ; 106         ;
; LAB Count - Fit Attempt 1                                                      ; 13          ;
; Outputs per Lab - Fit Attempt 1                                                ; 6.692       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 9.923       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.769       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:13        ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:13        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:12;1:1    ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:12;1:1    ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:8;1:4;2:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:8;1:4;2:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:12;1:1    ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:13        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:13        ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:8;2:5     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:8;1:5     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:13        ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:8;1:5     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:11;1:2    ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:12    ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:11;1:2    ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:13        ;
; LEs in Chains - Fit Attempt 1                                                  ; 41          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 11          ;
; LABs with Chains - Fit Attempt 1                                               ; 5           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
+--------------------------------------------------------------------------------+-------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 5      ;
; Early Slack - Fit Attempt 1         ; -23152 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 10     ;
; Mid Slack - Fit Attempt 1           ; -21153 ;
; Late Wire Use - Fit Attempt 1       ; 12     ;
; Late Slack - Fit Attempt 1          ; -21153 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.032  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -17715 ;
; Early Wire Use - Fit Attempt 1      ; 9      ;
; Peak Regional Wire - Fit Attempt 1  ; 8      ;
; Mid Slack - Fit Attempt 1           ; -20462 ;
; Late Slack - Fit Attempt 1          ; -20462 ;
; Late Wire Use - Fit Attempt 1       ; 13     ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.156  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jan 02 22:37:11 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_dis -c vga_dis
Info: Selected device EPM240T100C5 for design "vga_dis"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted signal "rst_n" to use Global clock
Info: Pin "rst_n" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 17.014 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y4; Fanout = 9; REG Node = 'x_cnt[0]'
    Info: 2: + IC(1.348 ns) + CELL(0.978 ns) = 2.326 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~300'
    Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.449 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~302'
    Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.572 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~298'
    Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.695 ns; Loc. = LAB_X4_Y4; Fanout = 2; COMB Node = 'Add2~293'
    Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 3.094 ns; Loc. = LAB_X4_Y4; Fanout = 5; COMB Node = 'Add2~295'
    Info: 7: + IC(0.000 ns) + CELL(1.234 ns) = 4.328 ns; Loc. = LAB_X4_Y4; Fanout = 4; COMB Node = 'Add2~307'
    Info: 8: + IC(1.360 ns) + CELL(0.914 ns) = 6.602 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'd_dis~352'
    Info: 9: + IC(1.069 ns) + CELL(0.511 ns) = 8.182 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'c_dis~128'
    Info: 10: + IC(0.440 ns) + CELL(0.740 ns) = 9.362 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'c_dis~129'
    Info: 11: + IC(0.980 ns) + CELL(0.200 ns) = 10.542 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'vga_b~25'
    Info: 12: + IC(0.266 ns) + CELL(0.914 ns) = 11.722 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'vga_b~26'
    Info: 13: + IC(0.266 ns) + CELL(0.914 ns) = 12.902 ns; Loc. = LAB_X4_Y3; Fanout = 1; COMB Node = 'vga_g~602'
    Info: 14: + IC(1.790 ns) + CELL(2.322 ns) = 17.014 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'vga_g'
    Info: Total cell delay = 9.495 ns ( 55.81 % )
    Info: Total interconnect delay = 7.519 ns ( 44.19 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 157 megabytes of memory during processing
    Info: Processing ended: Fri Jan 02 22:37:14 2009
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/个人项目/BJ-EPM240学习板/实验板刻盘资料/实验例程以及说明文档/7、VGA接口实验/verilogvga/vga_dis.fit.smsg.